[PATCH] D141054: [NVPTX] Set default version of architecture to SM_30, PTX to 6.0.

[Pavel Kopyl via Phabricator via llvm-commits]

pavelkopyl created this revision.
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Support of variadic functions triggers an assertion on several tests from
llvm/test/CodeGen/Generic/ if nvptx64-* is specified as a default triplet:
 "Support for variadic functions (unsized array parameter) introduced in

  PTX ISA version 6.0 and requires target sm_30."

That happens because those tests contain variadic function calls and default
versions of both PTX ISA (3.2) and architecture (sm_20) are below the minimally required.

There were no observable problems with these tests before adding support of variadic
functions, because nvptx backend just didn't handle them properly generating invalid PTX code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141054

Files:
  llvm/lib/Target/NVPTX/NVPTX.td
  llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
  llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll
  llvm/test/CodeGen/NVPTX/surf-tex.py
  llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll


Index: llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
===================================================================
--- llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
+++ llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda | FileCheck %s
 ; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64-nvidia-cuda | %ptxas-verify %}
 
-; CHECK: .target sm_20, debug
+; CHECK: .target sm_30, debug
 
 ; CHECK: .visible .func use_dbg_declare()
 ; CHECK: .local .align 8 .b8 __local_depot0[8];
Index: llvm/test/CodeGen/NVPTX/surf-tex.py
===================================================================
--- llvm/test/CodeGen/NVPTX/surf-tex.py
+++ llvm/test/CodeGen/NVPTX/surf-tex.py
@@ -1,6 +1,6 @@
 # RUN: %python %s --target=cuda --tests=suld,sust,tex,tld4 --gen-list=%t.list > %t-cuda.ll
-# RUN: llc %t-cuda.ll -verify-machineinstrs -o - | FileCheck %t-cuda.ll
-# RUN: %if ptxas %{ llc %t-cuda.ll -verify-machineinstrs -o - | %ptxas-verify %}
+# RUN: llc -mcpu=sm_20 %t-cuda.ll -verify-machineinstrs -o - | FileCheck %t-cuda.ll
+# RUN: %if ptxas %{ llc -mcpu=sm_20 %t-cuda.ll -verify-machineinstrs -o - | %ptxas-verify %}
 
 # We only need to run this second time for texture tests, because
 # there is a difference between unified and non-unified intrinsics.
Index: llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll
+++ llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll
@@ -1,7 +1,7 @@
 ; Libdevice in recent CUDA versions relies on __CUDA_ARCH reflecting GPU type.
 ; Verify that __nvvm_reflect() is replaced with an appropriate value.
 ;
-; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 \
+; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_20 \
 ; RUN:   | FileCheck %s --check-prefixes=COMMON,SM20
 ; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_35 \
 ; RUN:   | FileCheck %s --check-prefixes=COMMON,SM35
Index: llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+++ llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
@@ -33,13 +33,13 @@
 NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                                 StringRef FS) {
     // Provide the default CPU if we don't have one.
-    TargetName = std::string(CPU.empty() ? "sm_20" : CPU);
+    TargetName = std::string(CPU.empty() ? "sm_30" : CPU);
 
     ParseSubtargetFeatures(TargetName, /*TuneCPU*/ TargetName, FS);
 
-    // Set default to PTX 3.2 (CUDA 5.5)
+    // Set default to PTX 6.0 (CUDA 9.0)
     if (PTXVersion == 0) {
-      PTXVersion = 32;
+      PTXVersion = 60;
   }
 
   return *this;
Index: llvm/lib/Target/NVPTX/NVPTX.td
===================================================================
--- llvm/lib/Target/NVPTX/NVPTX.td
+++ llvm/lib/Target/NVPTX/NVPTX.td
@@ -115,11 +115,11 @@
 class Proc<string Name, list<SubtargetFeature> Features>
  : Processor<Name, NoItineraries, Features>;
 
-def : Proc<"sm_20", [SM20]>;
-def : Proc<"sm_21", [SM21]>;
-def : Proc<"sm_30", [SM30]>;
+def : Proc<"sm_20", [SM20, PTX32]>;
+def : Proc<"sm_21", [SM21, PTX32]>;
+def : Proc<"sm_30", [SM30, PTX32]>;
 def : Proc<"sm_32", [SM32, PTX40]>;
-def : Proc<"sm_35", [SM35]>;
+def : Proc<"sm_35", [SM35, PTX32]>;
 def : Proc<"sm_37", [SM37, PTX41]>;
 def : Proc<"sm_50", [SM50, PTX40]>;
 def : Proc<"sm_52", [SM52, PTX41]>;


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