[PATCH] D140938: [X86] Add tests for atomic bittest with register/memory operands

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/test/CodeGen/X86/atomic-rm-bit-test.ll:7392-7428
+; X86-LABEL: atomic_shl1_xor_64_gpr_val:
+; X86:       # %bb.0: # %entry
+; X86-NEXT:    pushl %ebp
+; X86-NEXT:    pushl %ebx
+; X86-NEXT:    pushl %edi
+; X86-NEXT:    pushl %esi
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
----------------
pengfei wrote:
> goldstein.w.n wrote:
> > pengfei wrote:
> > > I think we never have a chance to optimize 64-bit operations on 32-bits, right? Should we move these 64-bit tests to another file and only leave a single run `; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s`
> > > I think we never have a chance to optimize 64-bit operations on 32-bits, right? Should we move these 64-bit tests to another file and only leave a single run `; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s`
> > 
> > We get it something i.e:
> > ```
> > define zeroext i16 @atomic_shl1_or_16_const_val(ptr %v) nounwind {
> > ; X86-LABEL: atomic_shl1_or_16_const_val:
> > ; X86:       # %bb.0: # %entry
> > ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
> > ; X86-NEXT:    xorl %eax, %eax
> > ; X86-NEXT:    lock btsw $4, (%ecx)
> > ; X86-NEXT:    setb %al
> > ; X86-NEXT:    shll $4, %eax
> > ; X86-NEXT:    # kill: def $ax killed $ax killed $eax
> > ; X86-NEXT:    retl
> > ```
> I mean just put these `define i64 @...64...` into another file and only run for 64-bit.
Yes you probably want 2 files: atomic-rm-bit-test.ll (non-i64 tests tested on 32/64 triples) and atomic-rm-bit-test-x86_64.ll (i64 tests tested just on 64 triples).


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D140938/new/

https://reviews.llvm.org/D140938