[PATCH] D140907: [GlobalISel] New combine to commute constant operands to the RHS

[Jessica Del via Phabricator via llvm-commits]

OutOfCache added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll:53
 ; a 64 bit multiplication where the second argument was zero extended.
 define amdgpu_kernel void @v_mul_i64_zext_01(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
 ; GFX10-LABEL: v_mul_i64_zext_01:
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@tsymalla suggested in my revision to give the test cases more descriptive names.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll:258
 ; GFX10-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-NEXT:    v_mad_u64_u32 v[4:5], s0, 0, v0, 0
 ; GFX10-NEXT:    v_mul_lo_u32 v1, 0, v1
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This is a neat approach! Is there a possibility to extend this to `G_MAD` instructions as well? It's trickier since the operands don't have the same indices as for `G_MUL` etc. though.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll:312
 ; GFX10-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-NEXT:    v_mad_u64_u32 v[4:5], s0, v0, 0, 0
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
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`G_MAD` does not take advantage of the `binop_right_to_zero` rule.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll:386
 ; 64-bit multiplication, where the first argument is masked before a branch
 define amdgpu_kernel void @mul64_and_in_branch(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
 ; GFX10-LABEL: mul64_and_in_branch:
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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll:432
 ; 64-bit multiplication with both arguments changed in differnt basic blocks.
 define amdgpu_kernel void @mul64_and_in_branch_2(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) {
 ; GFX10-LABEL: mul64_and_in_branch_2:
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Repository:
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  https://reviews.llvm.org/D140907/new/

https://reviews.llvm.org/D140907