[PATCH] D140938: [X86] Add tests for atomic bittest with register/memory operands
Noah Goldstein via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 4 23:12:00 PST 2023
goldstein.w.n added inline comments.
================
Comment at: llvm/test/CodeGen/X86/atomic-rm-bit-test.ll:7392-7428
+; X86-LABEL: atomic_shl1_xor_64_gpr_val:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
----------------
pengfei wrote:
> I think we never have a chance to optimize 64-bit operations on 32-bits, right? Should we move these 64-bit tests to another file and only leave a single run `; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s`
> I think we never have a chance to optimize 64-bit operations on 32-bits, right? Should we move these 64-bit tests to another file and only leave a single run `; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s`
We get it something i.e:
```
define zeroext i16 @atomic_shl1_or_16_const_val(ptr %v) nounwind {
; X86-LABEL: atomic_shl1_or_16_const_val:
; X86: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: lock btsw $4, (%ecx)
; X86-NEXT: setb %al
; X86-NEXT: shll $4, %eax
; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl
```
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D140938/new/
https://reviews.llvm.org/D140938
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