[PATCH] D141022: [SelectionDAG] Improve codegen for udiv by constant if any divisors are 1.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: lebedev.ri, spatel, RKSimon, efriedma.
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If the divisor is 1, the magic algorithm does not return a correct
result and we end up using a select to pick the numerator for those
elements at the end.

Therefore we can use undef for that element of the earlier operations
when the divisor is 1. We sometimes get this through SimplifyDemandedVectorElts,
but not always. Definitely seems like we don't if the NPQ fixup is used.

Unfortunately, DAGCombiner is unable to fold srl X, <0, undef> to X so
I had to add flags to avoid emitting the srl unless one of the shift
amounts is non-zero.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141022

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
  llvm/test/CodeGen/X86/combine-udiv.ll

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