[PATCH] D140677: [AArch64][DAG] `canCombineShuffleToExtendVectorInreg()`: allow illegal types before legalization

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri marked an inline comment as done.
lebedev.ri added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll:473
 ; CHECK-NEXT:    cmp x8, #1000
-; CHECK-NEXT:    tbl.16b v3, { v2 }, v0
-; CHECK-NEXT:    tbl.16b v2, { v2 }, v1
-; CHECK-NEXT:    ucvtf.4s v3, v3
+; CHECK-NEXT:    dup.2s v2, v1[1]
+; CHECK-NEXT:    tbl.16b v1, { v1 }, v0
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lebedev.ri wrote:
> fhahn wrote:
> > I think this is not quite as clear cut as D140676, but I think this is still a regression over the original code where the constant-pool loads are outside the loop.
> I see. I'm still stomping out many many X86 regressions here,
> and didn't look into this AArch64-one.
> If someone else wants to, please feel free to do so?
Looks like that regression has been resolved, but other changes appeared.



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  https://reviews.llvm.org/D140677/new/

https://reviews.llvm.org/D140677