[PATCH] D140851: [Patch 3/4]: Add cases for assume (X & Y != {0|Y})

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


================
Comment at: llvm/lib/Analysis/ValueTracking.cpp:939
+        // 1. is_pow2(b) && b == a
+        //      v.zeros[log2(b)] = 1
+        // 2. is_pow2(b) && 0 == a
----------------
nikic wrote:
> It looks like we are missing this canonicalization: https://alive2.llvm.org/ce/z/MtveLU With that done, this becomes `v & b == 0` and is covered by existing handling.
> It looks like we are missing this canonicalization: https://alive2.llvm.org/ce/z/MtveLU With that done, this becomes `v & b == 0` and is covered by existing handling.

So would a better approach be to handle the `v & b != a` canonicalization in `InstCombine` and drop this case or leave this as is?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D140851/new/

https://reviews.llvm.org/D140851