[llvm] ac17b6b - [NFC] Autogenerate CodeGen/X86/sdiv-pow2.ll

[Amaury Séchet via llvm-commits]

Author: Amaury Séchet
Date: 2023-01-04T16:43:47Z
New Revision: ac17b6b963c4c610f99e52b579327660605a746a

URL: https://github.com/llvm/llvm-project/commit/ac17b6b963c4c610f99e52b579327660605a746a
DIFF: https://github.com/llvm/llvm-project/commit/ac17b6b963c4c610f99e52b579327660605a746a.diff

LOG: [NFC] Autogenerate CodeGen/X86/sdiv-pow2.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/sdiv-pow2.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/sdiv-pow2.ll b/llvm/test/CodeGen/X86/sdiv-pow2.ll
index d3042f6ca4ba8..66ea291c52d1a 100644
--- a/llvm/test/CodeGen/X86/sdiv-pow2.ll
+++ b/llvm/test/CodeGen/X86/sdiv-pow2.ll
@@ -1,33 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=i686-- < %s | FileCheck %s
 
 ; No attributes, should not use idiv
 define i32 @test1(i32 inreg %x) {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    sarl $31, %ecx
+; CHECK-NEXT:    shrl $28, %ecx
+; CHECK-NEXT:    addl %ecx, %eax
+; CHECK-NEXT:    sarl $4, %eax
+; CHECK-NEXT:    retl
 entry:
   %div = sdiv i32 %x, 16
   ret i32 %div
-; CHECK-LABEL: test1:
-; CHECK-NOT: idivl
-; CHECK: ret
 }
 
 ; Has minsize (-Oz) attribute, should generate idiv
 define i32 @test2(i32 inreg %x) minsize {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl $16
+; CHECK-NEXT:    .cfi_adjust_cfa_offset 4
+; CHECK-NEXT:    popl %ecx
+; CHECK-NEXT:    .cfi_adjust_cfa_offset -4
+; CHECK-NEXT:    cltd
+; CHECK-NEXT:    idivl %ecx
+; CHECK-NEXT:    retl
 entry:
   %div = sdiv i32 %x, 16
   ret i32 %div
-; CHECK-LABEL: test2:
-; CHECK: idivl
-; CHECK: ret
 }
 
 ; Has optsize (-Os) attribute, should not generate idiv
 define i32 @test3(i32 inreg %x) optsize {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    sarl $31, %ecx
+; CHECK-NEXT:    shrl $28, %ecx
+; CHECK-NEXT:    addl %ecx, %eax
+; CHECK-NEXT:    sarl $4, %eax
+; CHECK-NEXT:    retl
 entry:
   %div = sdiv i32 %x, 16
   ret i32 %div
-; CHECK-LABEL: test3:
-; CHECK-NOT: idivl
-; CHECK: ret
 }