[llvm] 28f21ca - [TypePromotion] Convert tests to opaque pointers (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 4 07:26:40 PST 2023
Author: Nikita Popov
Date: 2023-01-04T16:26:13+01:00
New Revision: 28f21cafdeac553039c9ae47a23df114c52bc27c
URL: https://github.com/llvm/llvm-project/commit/28f21cafdeac553039c9ae47a23df114c52bc27c
DIFF: https://github.com/llvm/llvm-project/commit/28f21cafdeac553039c9ae47a23df114c52bc27c.diff
LOG: [TypePromotion] Convert tests to opaque pointers (NFC)
Added:
Modified:
llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll
llvm/test/Transforms/TypePromotion/AArch64/loops.ll
llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll
llvm/test/Transforms/TypePromotion/ARM/calls.ll
llvm/test/Transforms/TypePromotion/ARM/casts.ll
llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll
llvm/test/Transforms/TypePromotion/ARM/icmps.ll
llvm/test/Transforms/TypePromotion/ARM/large-int.ll
llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
llvm/test/Transforms/TypePromotion/ARM/pointers.ll
llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll
llvm/test/Transforms/TypePromotion/ARM/signed.ll
llvm/test/Transforms/TypePromotion/ARM/switch.ll
llvm/test/Transforms/TypePromotion/ARM/wrapping.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll b/llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll
index 65db6cabf9d2f..0ed91efae669b 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll
@@ -6,31 +6,31 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
@_ZN4llvmL20trailingBytesForUTF8E = internal unnamed_addr constant [256 x i8] c"\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\03\03\03\03\03\03\03\03\04\04\04\04\05\05\05\05", align 1
@_ZN4llvmL15offsetsFromUTF8E = internal unnamed_addr constant [6 x i32] [i32 0, i32 12416, i32 925824, i32 63447168, i32 -100130688, i32 -2113396608], align 4
-define dso_local noundef i32 @_ZN4llvm18ConvertUTF8toUTF16EPPKhS1_PPtS3_NS_15ConversionFlagsE(i8** nocapture noundef %sourceStart, i8* noundef %sourceEnd, i16** nocapture noundef %targetStart, i16* noundef readnone %targetEnd, i32 noundef %flags) local_unnamed_addr {
+define dso_local noundef i32 @_ZN4llvm18ConvertUTF8toUTF16EPPKhS1_PPtS3_NS_15ConversionFlagsE(ptr nocapture noundef %sourceStart, ptr noundef %sourceEnd, ptr nocapture noundef %targetStart, ptr noundef readnone %targetEnd, i32 noundef %flags) local_unnamed_addr {
; CHECK-LABEL: @_ZN4llvm18ConvertUTF8toUTF16EPPKhS1_PPtS3_NS_15ConversionFlagsE(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[I:%.*]] = load i8*, i8** [[SOURCESTART:%.*]], align 8
-; CHECK-NEXT: [[I1:%.*]] = load i16*, i16** [[TARGETSTART:%.*]], align 8
-; CHECK-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i8* [[SOURCEEND:%.*]] to i64
+; CHECK-NEXT: [[I:%.*]] = load ptr, ptr [[SOURCESTART:%.*]], align 8
+; CHECK-NEXT: [[I1:%.*]] = load ptr, ptr [[TARGETSTART:%.*]], align 8
+; CHECK-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[SOURCEEND:%.*]] to i64
; CHECK-NEXT: [[CMP61:%.*]] = icmp eq i32 [[FLAGS:%.*]], 0
-; CHECK-NEXT: [[CMP183:%.*]] = icmp ult i8* [[I]], [[SOURCEEND]]
+; CHECK-NEXT: [[CMP183:%.*]] = icmp ult ptr [[I]], [[SOURCEEND]]
; CHECK-NEXT: br i1 [[CMP183]], label [[WHILE_BODY:%.*]], label [[WHILE_END:%.*]]
; CHECK: while.body:
-; CHECK-NEXT: [[TARGET_0186:%.*]] = phi i16* [ [[TARGET_2:%.*]], [[CLEANUP:%.*]] ], [ [[I1]], [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[SOURCE_0184:%.*]] = phi i8* [ [[SOURCE_6:%.*]], [[CLEANUP]] ], [ [[I]], [[ENTRY]] ]
-; CHECK-NEXT: [[I2:%.*]] = load i8, i8* [[SOURCE_0184]], align 1
+; CHECK-NEXT: [[TARGET_0186:%.*]] = phi ptr [ [[TARGET_2:%.*]], [[CLEANUP:%.*]] ], [ [[I1]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[SOURCE_0184:%.*]] = phi ptr [ [[SOURCE_6:%.*]], [[CLEANUP]] ], [ [[I]], [[ENTRY]] ]
+; CHECK-NEXT: [[I2:%.*]] = load i8, ptr [[SOURCE_0184]], align 1
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[I2]] to i32
; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP0]] to i64
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [256 x i8], [256 x i8]* @_ZN4llvmL20trailingBytesForUTF8E, i64 0, i64 [[IDXPROM]]
-; CHECK-NEXT: [[I3:%.*]] = load i8, i8* [[ARRAYIDX]], align 1
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [256 x i8], ptr @_ZN4llvmL20trailingBytesForUTF8E, i64 0, i64 [[IDXPROM]]
+; CHECK-NEXT: [[I3:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
; CHECK-NEXT: [[CONV1:%.*]] = zext i8 [[I3]] to i64
-; CHECK-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i8* [[SOURCE_0184]] to i64
+; CHECK-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[SOURCE_0184]] to i64
; CHECK-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp sgt i64 [[SUB_PTR_SUB]], [[CONV1]]
; CHECK-NEXT: br i1 [[CMP2_NOT]], label [[IF_END:%.*]], label [[WHILE_END]]
; CHECK: if.end:
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[CONV1]], 1
-; CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_0184]], i64 [[ADD]]
+; CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_0184]], i64 [[ADD]]
; CHECK-NEXT: switch i8 [[I3]], label [[WHILE_END]] [
; CHECK-NEXT: i8 3, label [[SW_BB_I:%.*]]
; CHECK-NEXT: i8 2, label [[SW_BB3_I:%.*]]
@@ -38,21 +38,21 @@ define dso_local noundef i32 @_ZN4llvm18ConvertUTF8toUTF16EPPKhS1_PPtS3_NS_15Con
; CHECK-NEXT: i8 0, label [[SW_BB47_I:%.*]]
; CHECK-NEXT: ]
; CHECK: sw.bb.i:
-; CHECK-NEXT: [[INCDEC_PTR_I:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_0184]], i64 [[CONV1]]
-; CHECK-NEXT: [[I4:%.*]] = load i8, i8* [[INCDEC_PTR_I]], align 1
+; CHECK-NEXT: [[INCDEC_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_0184]], i64 [[CONV1]]
+; CHECK-NEXT: [[I4:%.*]] = load i8, ptr [[INCDEC_PTR_I]], align 1
; CHECK-NEXT: [[I5:%.*]] = icmp sgt i8 [[I4]], -65
; CHECK-NEXT: br i1 [[I5]], label [[WHILE_END]], label [[SW_BB3_I]]
; CHECK: sw.bb3.i:
; CHECK-NEXT: [[I6:%.*]] = phi i64 [ [[ADD]], [[IF_END]] ], [ 3, [[SW_BB_I]] ]
-; CHECK-NEXT: [[I7:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_0184]], i64 -1
-; CHECK-NEXT: [[INCDEC_PTR4_I:%.*]] = getelementptr inbounds i8, i8* [[I7]], i64 [[I6]]
-; CHECK-NEXT: [[I8:%.*]] = load i8, i8* [[INCDEC_PTR4_I]], align 1
+; CHECK-NEXT: [[I7:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_0184]], i64 -1
+; CHECK-NEXT: [[INCDEC_PTR4_I:%.*]] = getelementptr inbounds i8, ptr [[I7]], i64 [[I6]]
+; CHECK-NEXT: [[I8:%.*]] = load i8, ptr [[INCDEC_PTR4_I]], align 1
; CHECK-NEXT: [[I9:%.*]] = icmp sgt i8 [[I8]], -65
; CHECK-NEXT: br i1 [[I9]], label [[WHILE_END]], label [[SW_BB12_I]]
; CHECK: sw.bb12.i:
-; CHECK-NEXT: [[SRCPTR_1_I:%.*]] = phi i8* [ [[ADD_PTR_I]], [[IF_END]] ], [ [[INCDEC_PTR4_I]], [[SW_BB3_I]] ]
-; CHECK-NEXT: [[INCDEC_PTR13_I:%.*]] = getelementptr inbounds i8, i8* [[SRCPTR_1_I]], i64 -1
-; CHECK-NEXT: [[I10:%.*]] = load i8, i8* [[INCDEC_PTR13_I]], align 1
+; CHECK-NEXT: [[SRCPTR_1_I:%.*]] = phi ptr [ [[ADD_PTR_I]], [[IF_END]] ], [ [[INCDEC_PTR4_I]], [[SW_BB3_I]] ]
+; CHECK-NEXT: [[INCDEC_PTR13_I:%.*]] = getelementptr inbounds i8, ptr [[SRCPTR_1_I]], i64 -1
+; CHECK-NEXT: [[I10:%.*]] = load i8, ptr [[INCDEC_PTR13_I]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[I10]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; CHECK-NEXT: [[I11:%.*]] = icmp sgt i8 [[TMP2]], -65
@@ -90,51 +90,51 @@ define dso_local noundef i32 @_ZN4llvm18ConvertUTF8toUTF16EPPKhS1_PPtS3_NS_15Con
; CHECK-NEXT: i8 2, label [[SW_BB19:%.*]]
; CHECK-NEXT: ]
; CHECK: sw.bb14:
-; CHECK-NEXT: [[INCDEC_PTR15:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_0184]], i64 1
+; CHECK-NEXT: [[INCDEC_PTR15:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_0184]], i64 1
; CHECK-NEXT: [[CONV16:%.*]] = zext i8 [[I2]] to i32
; CHECK-NEXT: [[SHL18:%.*]] = shl nuw nsw i32 [[CONV16]], 6
-; CHECK-NEXT: [[DOTPRE232:%.*]] = load i8, i8* [[INCDEC_PTR15]], align 1
+; CHECK-NEXT: [[DOTPRE232:%.*]] = load i8, ptr [[INCDEC_PTR15]], align 1
; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[DOTPRE232]] to i32
; CHECK-NEXT: br label [[SW_BB19]]
; CHECK: sw.bb19:
; CHECK-NEXT: [[I13:%.*]] = phi i32 [ [[TMP0]], [[IF_END5]] ], [ [[TMP4]], [[SW_BB14]] ]
-; CHECK-NEXT: [[SOURCE_3:%.*]] = phi i8* [ [[SOURCE_0184]], [[IF_END5]] ], [ [[INCDEC_PTR15]], [[SW_BB14]] ]
+; CHECK-NEXT: [[SOURCE_3:%.*]] = phi ptr [ [[SOURCE_0184]], [[IF_END5]] ], [ [[INCDEC_PTR15]], [[SW_BB14]] ]
; CHECK-NEXT: [[CH_2:%.*]] = phi i32 [ 0, [[IF_END5]] ], [ [[SHL18]], [[SW_BB14]] ]
-; CHECK-NEXT: [[INCDEC_PTR20:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_3]], i64 1
+; CHECK-NEXT: [[INCDEC_PTR20:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_3]], i64 1
; CHECK-NEXT: [[ADD22:%.*]] = add nuw nsw i32 [[CH_2]], [[I13]]
; CHECK-NEXT: [[SHL23:%.*]] = shl nsw i32 [[ADD22]], 6
-; CHECK-NEXT: [[DOTPRE233:%.*]] = load i8, i8* [[INCDEC_PTR20]], align 1
+; CHECK-NEXT: [[DOTPRE233:%.*]] = load i8, ptr [[INCDEC_PTR20]], align 1
; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[DOTPRE233]] to i32
; CHECK-NEXT: br label [[SW_BB24]]
; CHECK: sw.bb24:
; CHECK-NEXT: [[I14:%.*]] = phi i32 [ [[TMP0]], [[IF_END5]] ], [ [[TMP5]], [[SW_BB19]] ]
-; CHECK-NEXT: [[SOURCE_4:%.*]] = phi i8* [ [[SOURCE_0184]], [[IF_END5]] ], [ [[INCDEC_PTR20]], [[SW_BB19]] ]
+; CHECK-NEXT: [[SOURCE_4:%.*]] = phi ptr [ [[SOURCE_0184]], [[IF_END5]] ], [ [[INCDEC_PTR20]], [[SW_BB19]] ]
; CHECK-NEXT: [[CH_3:%.*]] = phi i32 [ 0, [[IF_END5]] ], [ [[SHL23]], [[SW_BB19]] ]
-; CHECK-NEXT: [[INCDEC_PTR25:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_4]], i64 1
+; CHECK-NEXT: [[INCDEC_PTR25:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_4]], i64 1
; CHECK-NEXT: [[ADD27:%.*]] = add nsw i32 [[CH_3]], [[I14]]
; CHECK-NEXT: [[SHL28:%.*]] = shl i32 [[ADD27]], 6
-; CHECK-NEXT: [[DOTPRE234:%.*]] = load i8, i8* [[INCDEC_PTR25]], align 1
+; CHECK-NEXT: [[DOTPRE234:%.*]] = load i8, ptr [[INCDEC_PTR25]], align 1
; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[DOTPRE234]] to i32
; CHECK-NEXT: br label [[SW_BB29]]
; CHECK: sw.bb29:
; CHECK-NEXT: [[I15:%.*]] = phi i32 [ [[TMP0]], [[IF_END5]] ], [ [[TMP6]], [[SW_BB24]] ]
-; CHECK-NEXT: [[SOURCE_5:%.*]] = phi i8* [ [[SOURCE_0184]], [[IF_END5]] ], [ [[INCDEC_PTR25]], [[SW_BB24]] ]
+; CHECK-NEXT: [[SOURCE_5:%.*]] = phi ptr [ [[SOURCE_0184]], [[IF_END5]] ], [ [[INCDEC_PTR25]], [[SW_BB24]] ]
; CHECK-NEXT: [[CH_4:%.*]] = phi i32 [ 0, [[IF_END5]] ], [ [[SHL28]], [[SW_BB24]] ]
-; CHECK-NEXT: [[INCDEC_PTR30:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_5]], i64 1
+; CHECK-NEXT: [[INCDEC_PTR30:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_5]], i64 1
; CHECK-NEXT: [[ADD32:%.*]] = add i32 [[CH_4]], [[I15]]
; CHECK-NEXT: br label [[SW_EPILOG]]
; CHECK: sw.epilog:
-; CHECK-NEXT: [[SOURCE_6]] = phi i8* [ [[SOURCE_0184]], [[IF_END5]] ], [ [[INCDEC_PTR30]], [[SW_BB29]] ]
+; CHECK-NEXT: [[SOURCE_6]] = phi ptr [ [[SOURCE_0184]], [[IF_END5]] ], [ [[INCDEC_PTR30]], [[SW_BB29]] ]
; CHECK-NEXT: [[CH_5:%.*]] = phi i32 [ 0, [[IF_END5]] ], [ [[ADD32]], [[SW_BB29]] ]
-; CHECK-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @_ZN4llvmL15offsetsFromUTF8E, i64 0, i64 [[CONV1]]
-; CHECK-NEXT: [[I16:%.*]] = load i32, i32* [[ARRAYIDX34]], align 4
+; CHECK-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [6 x i32], ptr @_ZN4llvmL15offsetsFromUTF8E, i64 0, i64 [[CONV1]]
+; CHECK-NEXT: [[I16:%.*]] = load i32, ptr [[ARRAYIDX34]], align 4
; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[CH_5]], [[I16]]
-; CHECK-NEXT: [[CMP35_NOT:%.*]] = icmp ult i16* [[TARGET_0186]], [[TARGETEND:%.*]]
+; CHECK-NEXT: [[CMP35_NOT:%.*]] = icmp ult ptr [[TARGET_0186]], [[TARGETEND:%.*]]
; CHECK-NEXT: br i1 [[CMP35_NOT]], label [[IF_END39:%.*]], label [[IF_THEN36:%.*]]
; CHECK: if.then36:
; CHECK-NEXT: [[CONV1_LE258:%.*]] = zext i8 [[I3]] to i64
; CHECK-NEXT: [[IDX_NEG:%.*]] = xor i64 [[CONV1_LE258]], -1
-; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_6]], i64 [[IDX_NEG]]
+; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_6]], i64 [[IDX_NEG]]
; CHECK-NEXT: br label [[WHILE_END]]
; CHECK: if.end39:
; CHECK-NEXT: [[CMP40:%.*]] = icmp ult i32 [[SUB]], 65536
@@ -148,16 +148,16 @@ define dso_local noundef i32 @_ZN4llvm18ConvertUTF8toUTF16EPPKhS1_PPtS3_NS_15Con
; CHECK: if.then46:
; CHECK-NEXT: [[CONV1_LE:%.*]] = zext i8 [[I3]] to i64
; CHECK-NEXT: [[IDX_NEG50:%.*]] = xor i64 [[CONV1_LE]], -1
-; CHECK-NEXT: [[ADD_PTR51:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_6]], i64 [[IDX_NEG50]]
+; CHECK-NEXT: [[ADD_PTR51:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_6]], i64 [[IDX_NEG50]]
; CHECK-NEXT: br label [[WHILE_END]]
; CHECK: if.else:
-; CHECK-NEXT: [[INCDEC_PTR52:%.*]] = getelementptr inbounds i16, i16* [[TARGET_0186]], i64 1
-; CHECK-NEXT: store i16 -3, i16* [[TARGET_0186]], align 2
+; CHECK-NEXT: [[INCDEC_PTR52:%.*]] = getelementptr inbounds i16, ptr [[TARGET_0186]], i64 1
+; CHECK-NEXT: store i16 -3, ptr [[TARGET_0186]], align 2
; CHECK-NEXT: br label [[CLEANUP]]
; CHECK: if.else54:
; CHECK-NEXT: [[CONV55:%.*]] = trunc i32 [[SUB]] to i16
-; CHECK-NEXT: [[INCDEC_PTR56:%.*]] = getelementptr inbounds i16, i16* [[TARGET_0186]], i64 1
-; CHECK-NEXT: store i16 [[CONV55]], i16* [[TARGET_0186]], align 2
+; CHECK-NEXT: [[INCDEC_PTR56:%.*]] = getelementptr inbounds i16, ptr [[TARGET_0186]], i64 1
+; CHECK-NEXT: store i16 [[CONV55]], ptr [[TARGET_0186]], align 2
; CHECK-NEXT: br label [[CLEANUP]]
; CHECK: if.else58:
; CHECK-NEXT: [[CMP59:%.*]] = icmp ugt i32 [[SUB]], 1114111
@@ -167,69 +167,69 @@ define dso_local noundef i32 @_ZN4llvm18ConvertUTF8toUTF16EPPKhS1_PPtS3_NS_15Con
; CHECK: if.then62:
; CHECK-NEXT: [[CONV1_LE254:%.*]] = zext i8 [[I3]] to i64
; CHECK-NEXT: [[IDX_NEG66:%.*]] = xor i64 [[CONV1_LE254]], -1
-; CHECK-NEXT: [[ADD_PTR67:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_6]], i64 [[IDX_NEG66]]
+; CHECK-NEXT: [[ADD_PTR67:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_6]], i64 [[IDX_NEG66]]
; CHECK-NEXT: br label [[WHILE_END]]
; CHECK: if.else68:
-; CHECK-NEXT: [[INCDEC_PTR69:%.*]] = getelementptr inbounds i16, i16* [[TARGET_0186]], i64 1
-; CHECK-NEXT: store i16 -3, i16* [[TARGET_0186]], align 2
+; CHECK-NEXT: [[INCDEC_PTR69:%.*]] = getelementptr inbounds i16, ptr [[TARGET_0186]], i64 1
+; CHECK-NEXT: store i16 -3, ptr [[TARGET_0186]], align 2
; CHECK-NEXT: br label [[CLEANUP]]
; CHECK: if.else71:
-; CHECK-NEXT: [[ADD_PTR72:%.*]] = getelementptr inbounds i16, i16* [[TARGET_0186]], i64 1
-; CHECK-NEXT: [[CMP73_NOT:%.*]] = icmp ult i16* [[ADD_PTR72]], [[TARGETEND]]
+; CHECK-NEXT: [[ADD_PTR72:%.*]] = getelementptr inbounds i16, ptr [[TARGET_0186]], i64 1
+; CHECK-NEXT: [[CMP73_NOT:%.*]] = icmp ult ptr [[ADD_PTR72]], [[TARGETEND]]
; CHECK-NEXT: br i1 [[CMP73_NOT]], label [[IF_END80:%.*]], label [[IF_THEN74:%.*]]
; CHECK: if.then74:
; CHECK-NEXT: [[CONV1_LE256:%.*]] = zext i8 [[I3]] to i64
; CHECK-NEXT: [[IDX_NEG78:%.*]] = xor i64 [[CONV1_LE256]], -1
-; CHECK-NEXT: [[ADD_PTR79:%.*]] = getelementptr inbounds i8, i8* [[SOURCE_6]], i64 [[IDX_NEG78]]
+; CHECK-NEXT: [[ADD_PTR79:%.*]] = getelementptr inbounds i8, ptr [[SOURCE_6]], i64 [[IDX_NEG78]]
; CHECK-NEXT: br label [[WHILE_END]]
; CHECK: if.end80:
; CHECK-NEXT: [[SUB81:%.*]] = add nuw nsw i32 [[SUB]], 67043328
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[SUB81]], 10
; CHECK-NEXT: [[I19:%.*]] = trunc i32 [[SHR]] to i16
; CHECK-NEXT: [[CONV83:%.*]] = add nuw nsw i16 [[I19]], -10240
-; CHECK-NEXT: store i16 [[CONV83]], i16* [[TARGET_0186]], align 2
+; CHECK-NEXT: store i16 [[CONV83]], ptr [[TARGET_0186]], align 2
; CHECK-NEXT: [[I20:%.*]] = trunc i32 [[SUB]] to i16
; CHECK-NEXT: [[I21:%.*]] = and i16 [[I20]], 1023
; CHECK-NEXT: [[CONV86:%.*]] = or i16 [[I21]], -9216
-; CHECK-NEXT: [[INCDEC_PTR87:%.*]] = getelementptr inbounds i16, i16* [[TARGET_0186]], i64 2
-; CHECK-NEXT: store i16 [[CONV86]], i16* [[ADD_PTR72]], align 2
+; CHECK-NEXT: [[INCDEC_PTR87:%.*]] = getelementptr inbounds i16, ptr [[TARGET_0186]], i64 2
+; CHECK-NEXT: store i16 [[CONV86]], ptr [[ADD_PTR72]], align 2
; CHECK-NEXT: br label [[CLEANUP]]
; CHECK: cleanup:
-; CHECK-NEXT: [[TARGET_2]] = phi i16* [ [[INCDEC_PTR52]], [[IF_ELSE]] ], [ [[INCDEC_PTR56]], [[IF_ELSE54]] ], [ [[INCDEC_PTR69]], [[IF_ELSE68]] ], [ [[INCDEC_PTR87]], [[IF_END80]] ]
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8* [[SOURCE_6]], [[SOURCEEND]]
+; CHECK-NEXT: [[TARGET_2]] = phi ptr [ [[INCDEC_PTR52]], [[IF_ELSE]] ], [ [[INCDEC_PTR56]], [[IF_ELSE54]] ], [ [[INCDEC_PTR69]], [[IF_ELSE68]] ], [ [[INCDEC_PTR87]], [[IF_END80]] ]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult ptr [[SOURCE_6]], [[SOURCEEND]]
; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END]]
; CHECK: while.end:
-; CHECK-NEXT: [[TARGET_0166:%.*]] = phi i16* [ [[TARGET_0186]], [[IF_THEN74]] ], [ [[TARGET_0186]], [[IF_THEN62]] ], [ [[TARGET_0186]], [[IF_THEN46]] ], [ [[TARGET_0186]], [[IF_THEN36]] ], [ [[I1]], [[ENTRY]] ], [ [[TARGET_2]], [[CLEANUP]] ], [ [[TARGET_0186]], [[WHILE_BODY]] ], [ [[TARGET_0186]], [[IF_END]] ], [ [[TARGET_0186]], [[SW_BB_I]] ], [ [[TARGET_0186]], [[SW_BB3_I]] ], [ [[TARGET_0186]], [[SW_BB12_I]] ], [ [[TARGET_0186]], [[SW_BB22_I]] ], [ [[TARGET_0186]], [[SW_BB27_I]] ], [ [[TARGET_0186]], [[SW_BB32_I]] ], [ [[TARGET_0186]], [[SW_BB37_I]] ], [ [[TARGET_0186]], [[SW_BB47_I]] ]
-; CHECK-NEXT: [[SOURCE_8:%.*]] = phi i8* [ [[ADD_PTR79]], [[IF_THEN74]] ], [ [[ADD_PTR67]], [[IF_THEN62]] ], [ [[ADD_PTR51]], [[IF_THEN46]] ], [ [[ADD_PTR]], [[IF_THEN36]] ], [ [[I]], [[ENTRY]] ], [ [[SOURCE_6]], [[CLEANUP]] ], [ [[SOURCE_0184]], [[WHILE_BODY]] ], [ [[SOURCE_0184]], [[IF_END]] ], [ [[SOURCE_0184]], [[SW_BB_I]] ], [ [[SOURCE_0184]], [[SW_BB3_I]] ], [ [[SOURCE_0184]], [[SW_BB12_I]] ], [ [[SOURCE_0184]], [[SW_BB22_I]] ], [ [[SOURCE_0184]], [[SW_BB27_I]] ], [ [[SOURCE_0184]], [[SW_BB32_I]] ], [ [[SOURCE_0184]], [[SW_BB37_I]] ], [ [[SOURCE_0184]], [[SW_BB47_I]] ]
+; CHECK-NEXT: [[TARGET_0166:%.*]] = phi ptr [ [[TARGET_0186]], [[IF_THEN74]] ], [ [[TARGET_0186]], [[IF_THEN62]] ], [ [[TARGET_0186]], [[IF_THEN46]] ], [ [[TARGET_0186]], [[IF_THEN36]] ], [ [[I1]], [[ENTRY]] ], [ [[TARGET_2]], [[CLEANUP]] ], [ [[TARGET_0186]], [[WHILE_BODY]] ], [ [[TARGET_0186]], [[IF_END]] ], [ [[TARGET_0186]], [[SW_BB_I]] ], [ [[TARGET_0186]], [[SW_BB3_I]] ], [ [[TARGET_0186]], [[SW_BB12_I]] ], [ [[TARGET_0186]], [[SW_BB22_I]] ], [ [[TARGET_0186]], [[SW_BB27_I]] ], [ [[TARGET_0186]], [[SW_BB32_I]] ], [ [[TARGET_0186]], [[SW_BB37_I]] ], [ [[TARGET_0186]], [[SW_BB47_I]] ]
+; CHECK-NEXT: [[SOURCE_8:%.*]] = phi ptr [ [[ADD_PTR79]], [[IF_THEN74]] ], [ [[ADD_PTR67]], [[IF_THEN62]] ], [ [[ADD_PTR51]], [[IF_THEN46]] ], [ [[ADD_PTR]], [[IF_THEN36]] ], [ [[I]], [[ENTRY]] ], [ [[SOURCE_6]], [[CLEANUP]] ], [ [[SOURCE_0184]], [[WHILE_BODY]] ], [ [[SOURCE_0184]], [[IF_END]] ], [ [[SOURCE_0184]], [[SW_BB_I]] ], [ [[SOURCE_0184]], [[SW_BB3_I]] ], [ [[SOURCE_0184]], [[SW_BB12_I]] ], [ [[SOURCE_0184]], [[SW_BB22_I]] ], [ [[SOURCE_0184]], [[SW_BB27_I]] ], [ [[SOURCE_0184]], [[SW_BB32_I]] ], [ [[SOURCE_0184]], [[SW_BB37_I]] ], [ [[SOURCE_0184]], [[SW_BB47_I]] ]
; CHECK-NEXT: [[RESULT_2:%.*]] = phi i32 [ 2, [[IF_THEN74]] ], [ 3, [[IF_THEN62]] ], [ 3, [[IF_THEN46]] ], [ 2, [[IF_THEN36]] ], [ 0, [[ENTRY]] ], [ 0, [[CLEANUP]] ], [ 1, [[WHILE_BODY]] ], [ 3, [[IF_END]] ], [ 3, [[SW_BB_I]] ], [ 3, [[SW_BB3_I]] ], [ 3, [[SW_BB12_I]] ], [ 3, [[SW_BB22_I]] ], [ 3, [[SW_BB27_I]] ], [ 3, [[SW_BB32_I]] ], [ 3, [[SW_BB37_I]] ], [ 3, [[SW_BB47_I]] ]
-; CHECK-NEXT: store i8* [[SOURCE_8]], i8** [[SOURCESTART]], align 8
-; CHECK-NEXT: store i16* [[TARGET_0166]], i16** [[TARGETSTART]], align 8
+; CHECK-NEXT: store ptr [[SOURCE_8]], ptr [[SOURCESTART]], align 8
+; CHECK-NEXT: store ptr [[TARGET_0166]], ptr [[TARGETSTART]], align 8
; CHECK-NEXT: ret i32 [[RESULT_2]]
;
entry:
- %i = load i8*, i8** %sourceStart, align 8
- %i1 = load i16*, i16** %targetStart, align 8
- %sub.ptr.lhs.cast = ptrtoint i8* %sourceEnd to i64
+ %i = load ptr, ptr %sourceStart, align 8
+ %i1 = load ptr, ptr %targetStart, align 8
+ %sub.ptr.lhs.cast = ptrtoint ptr %sourceEnd to i64
%cmp61 = icmp eq i32 %flags, 0
- %cmp183 = icmp ult i8* %i, %sourceEnd
+ %cmp183 = icmp ult ptr %i, %sourceEnd
br i1 %cmp183, label %while.body, label %while.end
while.body: ; preds = %cleanup, %entry
- %target.0186 = phi i16* [ %target.2, %cleanup ], [ %i1, %entry ]
- %source.0184 = phi i8* [ %source.6, %cleanup ], [ %i, %entry ]
- %i2 = load i8, i8* %source.0184, align 1
+ %target.0186 = phi ptr [ %target.2, %cleanup ], [ %i1, %entry ]
+ %source.0184 = phi ptr [ %source.6, %cleanup ], [ %i, %entry ]
+ %i2 = load i8, ptr %source.0184, align 1
%idxprom = zext i8 %i2 to i64
- %arrayidx = getelementptr inbounds [256 x i8], [256 x i8]* @_ZN4llvmL20trailingBytesForUTF8E, i64 0, i64 %idxprom
- %i3 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds [256 x i8], ptr @_ZN4llvmL20trailingBytesForUTF8E, i64 0, i64 %idxprom
+ %i3 = load i8, ptr %arrayidx, align 1
%conv1 = zext i8 %i3 to i64
- %sub.ptr.rhs.cast = ptrtoint i8* %source.0184 to i64
+ %sub.ptr.rhs.cast = ptrtoint ptr %source.0184 to i64
%sub.ptr.sub = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast
%cmp2.not = icmp sgt i64 %sub.ptr.sub, %conv1
br i1 %cmp2.not, label %if.end, label %while.end
if.end: ; preds = %while.body
%add = add nuw nsw i64 %conv1, 1
- %add.ptr.i = getelementptr inbounds i8, i8* %source.0184, i64 %add
+ %add.ptr.i = getelementptr inbounds i8, ptr %source.0184, i64 %add
switch i8 %i3, label %while.end [
i8 3, label %sw.bb.i
i8 2, label %sw.bb3.i
@@ -238,23 +238,23 @@ if.end: ; preds = %while.body
]
sw.bb.i: ; preds = %if.end
- %incdec.ptr.i = getelementptr inbounds i8, i8* %source.0184, i64 %conv1
- %i4 = load i8, i8* %incdec.ptr.i, align 1
+ %incdec.ptr.i = getelementptr inbounds i8, ptr %source.0184, i64 %conv1
+ %i4 = load i8, ptr %incdec.ptr.i, align 1
%i5 = icmp sgt i8 %i4, -65
br i1 %i5, label %while.end, label %sw.bb3.i
sw.bb3.i: ; preds = %sw.bb.i, %if.end
%i6 = phi i64 [ %add, %if.end ], [ 3, %sw.bb.i ]
- %i7 = getelementptr inbounds i8, i8* %source.0184, i64 -1
- %incdec.ptr4.i = getelementptr inbounds i8, i8* %i7, i64 %i6
- %i8 = load i8, i8* %incdec.ptr4.i, align 1
+ %i7 = getelementptr inbounds i8, ptr %source.0184, i64 -1
+ %incdec.ptr4.i = getelementptr inbounds i8, ptr %i7, i64 %i6
+ %i8 = load i8, ptr %incdec.ptr4.i, align 1
%i9 = icmp sgt i8 %i8, -65
br i1 %i9, label %while.end, label %sw.bb12.i
sw.bb12.i: ; preds = %sw.bb3.i, %if.end
- %srcptr.1.i = phi i8* [ %add.ptr.i, %if.end ], [ %incdec.ptr4.i, %sw.bb3.i ]
- %incdec.ptr13.i = getelementptr inbounds i8, i8* %srcptr.1.i, i64 -1
- %i10 = load i8, i8* %incdec.ptr13.i, align 1
+ %srcptr.1.i = phi ptr [ %add.ptr.i, %if.end ], [ %incdec.ptr4.i, %sw.bb3.i ]
+ %incdec.ptr13.i = getelementptr inbounds i8, ptr %srcptr.1.i, i64 -1
+ %i10 = load i8, ptr %incdec.ptr13.i, align 1
%i11 = icmp sgt i8 %i10, -65
br i1 %i11, label %while.end, label %if.end20.i
@@ -297,56 +297,56 @@ if.end5: ; preds = %sw.bb47.i, %sw.bb37
]
sw.bb14: ; preds = %if.end5
- %incdec.ptr15 = getelementptr inbounds i8, i8* %source.0184, i64 1
+ %incdec.ptr15 = getelementptr inbounds i8, ptr %source.0184, i64 1
%conv16 = zext i8 %i2 to i32
%shl18 = shl nuw nsw i32 %conv16, 6
- %.pre232 = load i8, i8* %incdec.ptr15, align 1
+ %.pre232 = load i8, ptr %incdec.ptr15, align 1
br label %sw.bb19
sw.bb19: ; preds = %sw.bb14, %if.end5
%i13 = phi i8 [ %i2, %if.end5 ], [ %.pre232, %sw.bb14 ]
- %source.3 = phi i8* [ %source.0184, %if.end5 ], [ %incdec.ptr15, %sw.bb14 ]
+ %source.3 = phi ptr [ %source.0184, %if.end5 ], [ %incdec.ptr15, %sw.bb14 ]
%ch.2 = phi i32 [ 0, %if.end5 ], [ %shl18, %sw.bb14 ]
- %incdec.ptr20 = getelementptr inbounds i8, i8* %source.3, i64 1
+ %incdec.ptr20 = getelementptr inbounds i8, ptr %source.3, i64 1
%conv21 = zext i8 %i13 to i32
%add22 = add nuw nsw i32 %ch.2, %conv21
%shl23 = shl nsw i32 %add22, 6
- %.pre233 = load i8, i8* %incdec.ptr20, align 1
+ %.pre233 = load i8, ptr %incdec.ptr20, align 1
br label %sw.bb24
sw.bb24: ; preds = %sw.bb19, %if.end5
%i14 = phi i8 [ %i2, %if.end5 ], [ %.pre233, %sw.bb19 ]
- %source.4 = phi i8* [ %source.0184, %if.end5 ], [ %incdec.ptr20, %sw.bb19 ]
+ %source.4 = phi ptr [ %source.0184, %if.end5 ], [ %incdec.ptr20, %sw.bb19 ]
%ch.3 = phi i32 [ 0, %if.end5 ], [ %shl23, %sw.bb19 ]
- %incdec.ptr25 = getelementptr inbounds i8, i8* %source.4, i64 1
+ %incdec.ptr25 = getelementptr inbounds i8, ptr %source.4, i64 1
%conv26 = zext i8 %i14 to i32
%add27 = add nsw i32 %ch.3, %conv26
%shl28 = shl i32 %add27, 6
- %.pre234 = load i8, i8* %incdec.ptr25, align 1
+ %.pre234 = load i8, ptr %incdec.ptr25, align 1
br label %sw.bb29
sw.bb29: ; preds = %sw.bb24, %if.end5
%i15 = phi i8 [ %i2, %if.end5 ], [ %.pre234, %sw.bb24 ]
- %source.5 = phi i8* [ %source.0184, %if.end5 ], [ %incdec.ptr25, %sw.bb24 ]
+ %source.5 = phi ptr [ %source.0184, %if.end5 ], [ %incdec.ptr25, %sw.bb24 ]
%ch.4 = phi i32 [ 0, %if.end5 ], [ %shl28, %sw.bb24 ]
- %incdec.ptr30 = getelementptr inbounds i8, i8* %source.5, i64 1
+ %incdec.ptr30 = getelementptr inbounds i8, ptr %source.5, i64 1
%conv31 = zext i8 %i15 to i32
%add32 = add i32 %ch.4, %conv31
br label %sw.epilog
sw.epilog: ; preds = %sw.bb29, %if.end5
- %source.6 = phi i8* [ %source.0184, %if.end5 ], [ %incdec.ptr30, %sw.bb29 ]
+ %source.6 = phi ptr [ %source.0184, %if.end5 ], [ %incdec.ptr30, %sw.bb29 ]
%ch.5 = phi i32 [ 0, %if.end5 ], [ %add32, %sw.bb29 ]
- %arrayidx34 = getelementptr inbounds [6 x i32], [6 x i32]* @_ZN4llvmL15offsetsFromUTF8E, i64 0, i64 %conv1
- %i16 = load i32, i32* %arrayidx34, align 4
+ %arrayidx34 = getelementptr inbounds [6 x i32], ptr @_ZN4llvmL15offsetsFromUTF8E, i64 0, i64 %conv1
+ %i16 = load i32, ptr %arrayidx34, align 4
%sub = sub i32 %ch.5, %i16
- %cmp35.not = icmp ult i16* %target.0186, %targetEnd
+ %cmp35.not = icmp ult ptr %target.0186, %targetEnd
br i1 %cmp35.not, label %if.end39, label %if.then36
if.then36: ; preds = %sw.epilog
%conv1.le258 = zext i8 %i3 to i64
%idx.neg = xor i64 %conv1.le258, -1
- %add.ptr = getelementptr inbounds i8, i8* %source.6, i64 %idx.neg
+ %add.ptr = getelementptr inbounds i8, ptr %source.6, i64 %idx.neg
br label %while.end
if.end39: ; preds = %sw.epilog
@@ -364,18 +364,18 @@ if.then44: ; preds = %if.then41
if.then46: ; preds = %if.then44
%conv1.le = zext i8 %i3 to i64
%idx.neg50 = xor i64 %conv1.le, -1
- %add.ptr51 = getelementptr inbounds i8, i8* %source.6, i64 %idx.neg50
+ %add.ptr51 = getelementptr inbounds i8, ptr %source.6, i64 %idx.neg50
br label %while.end
if.else: ; preds = %if.then44
- %incdec.ptr52 = getelementptr inbounds i16, i16* %target.0186, i64 1
- store i16 -3, i16* %target.0186, align 2
+ %incdec.ptr52 = getelementptr inbounds i16, ptr %target.0186, i64 1
+ store i16 -3, ptr %target.0186, align 2
br label %cleanup
if.else54: ; preds = %if.then41
%conv55 = trunc i32 %sub to i16
- %incdec.ptr56 = getelementptr inbounds i16, i16* %target.0186, i64 1
- store i16 %conv55, i16* %target.0186, align 2
+ %incdec.ptr56 = getelementptr inbounds i16, ptr %target.0186, i64 1
+ store i16 %conv55, ptr %target.0186, align 2
br label %cleanup
if.else58: ; preds = %if.end39
@@ -388,23 +388,23 @@ if.then60: ; preds = %if.else58
if.then62: ; preds = %if.then60
%conv1.le254 = zext i8 %i3 to i64
%idx.neg66 = xor i64 %conv1.le254, -1
- %add.ptr67 = getelementptr inbounds i8, i8* %source.6, i64 %idx.neg66
+ %add.ptr67 = getelementptr inbounds i8, ptr %source.6, i64 %idx.neg66
br label %while.end
if.else68: ; preds = %if.then60
- %incdec.ptr69 = getelementptr inbounds i16, i16* %target.0186, i64 1
- store i16 -3, i16* %target.0186, align 2
+ %incdec.ptr69 = getelementptr inbounds i16, ptr %target.0186, i64 1
+ store i16 -3, ptr %target.0186, align 2
br label %cleanup
if.else71: ; preds = %if.else58
- %add.ptr72 = getelementptr inbounds i16, i16* %target.0186, i64 1
- %cmp73.not = icmp ult i16* %add.ptr72, %targetEnd
+ %add.ptr72 = getelementptr inbounds i16, ptr %target.0186, i64 1
+ %cmp73.not = icmp ult ptr %add.ptr72, %targetEnd
br i1 %cmp73.not, label %if.end80, label %if.then74
if.then74: ; preds = %if.else71
%conv1.le256 = zext i8 %i3 to i64
%idx.neg78 = xor i64 %conv1.le256, -1
- %add.ptr79 = getelementptr inbounds i8, i8* %source.6, i64 %idx.neg78
+ %add.ptr79 = getelementptr inbounds i8, ptr %source.6, i64 %idx.neg78
br label %while.end
if.end80: ; preds = %if.else71
@@ -412,24 +412,24 @@ if.end80: ; preds = %if.else71
%shr = lshr i32 %sub81, 10
%i19 = trunc i32 %shr to i16
%conv83 = add nuw nsw i16 %i19, -10240
- store i16 %conv83, i16* %target.0186, align 2
+ store i16 %conv83, ptr %target.0186, align 2
%i20 = trunc i32 %sub to i16
%i21 = and i16 %i20, 1023
%conv86 = or i16 %i21, -9216
- %incdec.ptr87 = getelementptr inbounds i16, i16* %target.0186, i64 2
- store i16 %conv86, i16* %add.ptr72, align 2
+ %incdec.ptr87 = getelementptr inbounds i16, ptr %target.0186, i64 2
+ store i16 %conv86, ptr %add.ptr72, align 2
br label %cleanup
cleanup: ; preds = %if.end80, %if.else68, %if.else54, %if.else
- %target.2 = phi i16* [ %incdec.ptr52, %if.else ], [ %incdec.ptr56, %if.else54 ], [ %incdec.ptr69, %if.else68 ], [ %incdec.ptr87, %if.end80 ]
- %cmp = icmp ult i8* %source.6, %sourceEnd
+ %target.2 = phi ptr [ %incdec.ptr52, %if.else ], [ %incdec.ptr56, %if.else54 ], [ %incdec.ptr69, %if.else68 ], [ %incdec.ptr87, %if.end80 ]
+ %cmp = icmp ult ptr %source.6, %sourceEnd
br i1 %cmp, label %while.body, label %while.end
while.end: ; preds = %cleanup, %if.then74, %if.then62, %if.then46, %if.then36, %sw.bb47.i, %sw.bb37.i, %sw.bb32.i, %sw.bb27.i, %sw.bb22.i, %sw.bb12.i, %sw.bb3.i, %sw.bb.i, %if.end, %while.body, %entry
- %target.0166 = phi i16* [ %target.0186, %if.then74 ], [ %target.0186, %if.then62 ], [ %target.0186, %if.then46 ], [ %target.0186, %if.then36 ], [ %i1, %entry ], [ %target.2, %cleanup ], [ %target.0186, %while.body ], [ %target.0186, %if.end ], [ %target.0186, %sw.bb.i ], [ %target.0186, %sw.bb3.i ], [ %target.0186, %sw.bb12.i ], [ %target.0186, %sw.bb22.i ], [ %target.0186, %sw.bb27.i ], [ %target.0186, %sw.bb32.i ], [ %target.0186, %sw.bb37.i ], [ %target.0186, %sw.bb47.i ]
- %source.8 = phi i8* [ %add.ptr79, %if.then74 ], [ %add.ptr67, %if.then62 ], [ %add.ptr51, %if.then46 ], [ %add.ptr, %if.then36 ], [ %i, %entry ], [ %source.6, %cleanup ], [ %source.0184, %while.body ], [ %source.0184, %if.end ], [ %source.0184, %sw.bb.i ], [ %source.0184, %sw.bb3.i ], [ %source.0184, %sw.bb12.i ], [ %source.0184, %sw.bb22.i ], [ %source.0184, %sw.bb27.i ], [ %source.0184, %sw.bb32.i ], [ %source.0184, %sw.bb37.i ], [ %source.0184, %sw.bb47.i ]
+ %target.0166 = phi ptr [ %target.0186, %if.then74 ], [ %target.0186, %if.then62 ], [ %target.0186, %if.then46 ], [ %target.0186, %if.then36 ], [ %i1, %entry ], [ %target.2, %cleanup ], [ %target.0186, %while.body ], [ %target.0186, %if.end ], [ %target.0186, %sw.bb.i ], [ %target.0186, %sw.bb3.i ], [ %target.0186, %sw.bb12.i ], [ %target.0186, %sw.bb22.i ], [ %target.0186, %sw.bb27.i ], [ %target.0186, %sw.bb32.i ], [ %target.0186, %sw.bb37.i ], [ %target.0186, %sw.bb47.i ]
+ %source.8 = phi ptr [ %add.ptr79, %if.then74 ], [ %add.ptr67, %if.then62 ], [ %add.ptr51, %if.then46 ], [ %add.ptr, %if.then36 ], [ %i, %entry ], [ %source.6, %cleanup ], [ %source.0184, %while.body ], [ %source.0184, %if.end ], [ %source.0184, %sw.bb.i ], [ %source.0184, %sw.bb3.i ], [ %source.0184, %sw.bb12.i ], [ %source.0184, %sw.bb22.i ], [ %source.0184, %sw.bb27.i ], [ %source.0184, %sw.bb32.i ], [ %source.0184, %sw.bb37.i ], [ %source.0184, %sw.bb47.i ]
%result.2 = phi i32 [ 2, %if.then74 ], [ 3, %if.then62 ], [ 3, %if.then46 ], [ 2, %if.then36 ], [ 0, %entry ], [ 0, %cleanup ], [ 1, %while.body ], [ 3, %if.end ], [ 3, %sw.bb.i ], [ 3, %sw.bb3.i ], [ 3, %sw.bb12.i ], [ 3, %sw.bb22.i ], [ 3, %sw.bb27.i ], [ 3, %sw.bb32.i ], [ 3, %sw.bb37.i ], [ 3, %sw.bb47.i ]
- store i8* %source.8, i8** %sourceStart, align 8
- store i16* %target.0166, i16** %targetStart, align 8
+ store ptr %source.8, ptr %sourceStart, align 8
+ store ptr %target.0166, ptr %targetStart, align 8
ret i32 %result.2
}
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/loops.ll b/llvm/test/Transforms/TypePromotion/AArch64/loops.ll
index 07acd49d432fa..bbc972505f0e0 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/loops.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/loops.ll
@@ -3,10 +3,10 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-define dso_local i32 @ic_strcmp(i8* nocapture readonly %arg, i8* nocapture readonly %arg1) {
+define dso_local i32 @ic_strcmp(ptr nocapture readonly %arg, ptr nocapture readonly %arg1) {
; CHECK-LABEL: @ic_strcmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = load i8, i8* [[ARG:%.*]], align 1
+; CHECK-NEXT: [[I:%.*]] = load i8, ptr [[ARG:%.*]], align 1
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[I]] to i32
; CHECK-NEXT: [[I2:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK-NEXT: br i1 [[I2]], label [[BB25:%.*]], label [[BB3:%.*]]
@@ -14,8 +14,8 @@ define dso_local i32 @ic_strcmp(i8* nocapture readonly %arg, i8* nocapture reado
; CHECK-NEXT: [[I4:%.*]] = phi i64 [ [[I16:%.*]], [[BB15:%.*]] ], [ 0, [[BB:%.*]] ]
; CHECK-NEXT: [[I5:%.*]] = phi i32 [ [[TMP2:%.*]], [[BB15]] ], [ [[TMP0]], [[BB]] ]
; CHECK-NEXT: [[I6:%.*]] = phi i32 [ [[I17:%.*]], [[BB15]] ], [ 0, [[BB]] ]
-; CHECK-NEXT: [[I7:%.*]] = getelementptr inbounds i8, i8* [[ARG1:%.*]], i64 [[I4]]
-; CHECK-NEXT: [[I8:%.*]] = load i8, i8* [[I7]], align 1
+; CHECK-NEXT: [[I7:%.*]] = getelementptr inbounds i8, ptr [[ARG1:%.*]], i64 [[I4]]
+; CHECK-NEXT: [[I8:%.*]] = load i8, ptr [[I7]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[I8]] to i32
; CHECK-NEXT: [[I9:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: br i1 [[I9]], label [[BB23:%.*]], label [[BB10:%.*]]
@@ -28,8 +28,8 @@ define dso_local i32 @ic_strcmp(i8* nocapture readonly %arg, i8* nocapture reado
; CHECK: bb15:
; CHECK-NEXT: [[I16]] = add nuw i64 [[I4]], 1
; CHECK-NEXT: [[I17]] = add nuw nsw i32 [[I6]], 1
-; CHECK-NEXT: [[I18:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 [[I16]]
-; CHECK-NEXT: [[I19:%.*]] = load i8, i8* [[I18]], align 1
+; CHECK-NEXT: [[I18:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 [[I16]]
+; CHECK-NEXT: [[I19:%.*]] = load i8, ptr [[I18]], align 1
; CHECK-NEXT: [[TMP2]] = zext i8 [[I19]] to i32
; CHECK-NEXT: [[I20:%.*]] = icmp eq i32 [[TMP2]], 0
; CHECK-NEXT: br i1 [[I20]], label [[BB25]], label [[BB3]]
@@ -43,8 +43,8 @@ define dso_local i32 @ic_strcmp(i8* nocapture readonly %arg, i8* nocapture reado
; CHECK-NEXT: [[I26:%.*]] = phi i32 [ 0, [[BB]] ], [ [[I22]], [[BB21]] ], [ [[I24]], [[BB23]] ], [ [[I17]], [[BB15]] ]
; CHECK-NEXT: [[I27:%.*]] = phi i32 [ 0, [[BB]] ], [ [[I5]], [[BB21]] ], [ [[I5]], [[BB23]] ], [ 0, [[BB15]] ]
; CHECK-NEXT: [[I28:%.*]] = zext i32 [[I26]] to i64
-; CHECK-NEXT: [[I29:%.*]] = getelementptr inbounds i8, i8* [[ARG1]], i64 [[I28]]
-; CHECK-NEXT: [[I30:%.*]] = load i8, i8* [[I29]], align 1
+; CHECK-NEXT: [[I29:%.*]] = getelementptr inbounds i8, ptr [[ARG1]], i64 [[I28]]
+; CHECK-NEXT: [[I30:%.*]] = load i8, ptr [[I29]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[I30]] to i32
; CHECK-NEXT: [[I31:%.*]] = icmp eq i32 [[I27]], [[TMP3]]
; CHECK-NEXT: [[I32:%.*]] = or i32 [[I27]], 32
@@ -55,7 +55,7 @@ define dso_local i32 @ic_strcmp(i8* nocapture readonly %arg, i8* nocapture reado
; CHECK-NEXT: ret i32 [[I36]]
;
bb:
- %i = load i8, i8* %arg, align 1
+ %i = load i8, ptr %arg, align 1
%i2 = icmp eq i8 %i, 0
br i1 %i2, label %bb25, label %bb3
@@ -63,8 +63,8 @@ bb3: ; preds = %bb15, %bb
%i4 = phi i64 [ %i16, %bb15 ], [ 0, %bb ]
%i5 = phi i8 [ %i19, %bb15 ], [ %i, %bb ]
%i6 = phi i32 [ %i17, %bb15 ], [ 0, %bb ]
- %i7 = getelementptr inbounds i8, i8* %arg1, i64 %i4
- %i8 = load i8, i8* %i7, align 1
+ %i7 = getelementptr inbounds i8, ptr %arg1, i64 %i4
+ %i8 = load i8, ptr %i7, align 1
%i9 = icmp eq i8 %i8, 0
br i1 %i9, label %bb23, label %bb10
@@ -78,8 +78,8 @@ bb10: ; preds = %bb3
bb15: ; preds = %bb10
%i16 = add nuw i64 %i4, 1
%i17 = add nuw nsw i32 %i6, 1
- %i18 = getelementptr inbounds i8, i8* %arg, i64 %i16
- %i19 = load i8, i8* %i18, align 1
+ %i18 = getelementptr inbounds i8, ptr %arg, i64 %i16
+ %i19 = load i8, ptr %i18, align 1
%i20 = icmp eq i8 %i19, 0
br i1 %i20, label %bb25, label %bb3
@@ -95,8 +95,8 @@ bb25: ; preds = %bb23, %bb21, %bb15,
%i26 = phi i32 [ 0, %bb ], [ %i22, %bb21 ], [ %i24, %bb23 ], [ %i17, %bb15 ]
%i27 = phi i8 [ 0, %bb ], [ %i5, %bb21 ], [ %i5, %bb23 ], [ 0, %bb15 ]
%i28 = zext i32 %i26 to i64
- %i29 = getelementptr inbounds i8, i8* %arg1, i64 %i28
- %i30 = load i8, i8* %i29, align 1
+ %i29 = getelementptr inbounds i8, ptr %arg1, i64 %i28
+ %i30 = load i8, ptr %i29, align 1
%i31 = icmp eq i8 %i27, %i30
%i32 = or i8 %i27, 32
%i33 = or i8 %i30, 32
@@ -106,10 +106,10 @@ bb25: ; preds = %bb23, %bb21, %bb15,
ret i32 %i36
}
-define dso_local i16 @i16_loop_add_i8(i8* nocapture readonly %arg) {
+define dso_local i16 @i16_loop_add_i8(ptr nocapture readonly %arg) {
; CHECK-LABEL: @i16_loop_add_i8(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = load i8, i8* [[ARG:%.*]], align 1
+; CHECK-NEXT: [[I:%.*]] = load i8, ptr [[ARG:%.*]], align 1
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[I]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
; CHECK-NEXT: [[I1:%.*]] = zext i8 [[TMP1]] to i16
@@ -121,8 +121,8 @@ define dso_local i16 @i16_loop_add_i8(i8* nocapture readonly %arg) {
; CHECK-NEXT: [[I6:%.*]] = phi i16 [ [[I12:%.*]], [[BB4]] ], [ [[I1]], [[BB]] ]
; CHECK-NEXT: [[I7]] = add i32 [[I5]], 1
; CHECK-NEXT: [[I8:%.*]] = zext i32 [[I7]] to i64
-; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 [[I8]]
-; CHECK-NEXT: [[I10:%.*]] = load i8, i8* [[I9]], align 1
+; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 [[I8]]
+; CHECK-NEXT: [[I10:%.*]] = load i8, ptr [[I9]], align 1
; CHECK-NEXT: [[I11:%.*]] = zext i8 [[I10]] to i16
; CHECK-NEXT: [[I12]] = add nuw nsw i16 [[I6]], [[I11]]
; CHECK-NEXT: [[I13:%.*]] = icmp ne i8 [[I10]], 0
@@ -134,7 +134,7 @@ define dso_local i16 @i16_loop_add_i8(i8* nocapture readonly %arg) {
; CHECK-NEXT: ret i16 [[I17]]
;
bb:
- %i = load i8, i8* %arg, align 1
+ %i = load i8, ptr %arg, align 1
%i1 = zext i8 %i to i16
%i2 = add i8 %i, -1
%i3 = icmp ult i8 %i2, 31
@@ -145,8 +145,8 @@ bb4: ; preds = %bb4, %bb
%i6 = phi i16 [ %i12, %bb4 ], [ %i1, %bb ]
%i7 = add i32 %i5, 1
%i8 = zext i32 %i7 to i64
- %i9 = getelementptr inbounds i8, i8* %arg, i64 %i8
- %i10 = load i8, i8* %i9, align 1
+ %i9 = getelementptr inbounds i8, ptr %arg, i64 %i8
+ %i10 = load i8, ptr %i9, align 1
%i11 = zext i8 %i10 to i16
%i12 = add nuw nsw i16 %i6, %i11
%i13 = icmp ne i8 %i10, 0
@@ -159,10 +159,10 @@ bb16: ; preds = %bb4, %bb
ret i16 %i17
}
-define dso_local i32 @i32_loop_add_i16(i16* nocapture readonly %arg) {
+define dso_local i32 @i32_loop_add_i16(ptr nocapture readonly %arg) {
; CHECK-LABEL: @i32_loop_add_i16(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = load i16, i16* [[ARG:%.*]], align 2
+; CHECK-NEXT: [[I:%.*]] = load i16, ptr [[ARG:%.*]], align 2
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[I]] to i32
; CHECK-NEXT: [[I1:%.*]] = zext i16 [[I]] to i32
; CHECK-NEXT: [[I2:%.*]] = add i32 [[TMP0]], -1
@@ -173,8 +173,8 @@ define dso_local i32 @i32_loop_add_i16(i16* nocapture readonly %arg) {
; CHECK-NEXT: [[I6:%.*]] = phi i32 [ [[I12:%.*]], [[BB4]] ], [ [[I1]], [[BB]] ]
; CHECK-NEXT: [[I7]] = add i32 [[I5]], 1
; CHECK-NEXT: [[I8:%.*]] = zext i32 [[I7]] to i64
-; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i16, i16* [[ARG]], i64 [[I8]]
-; CHECK-NEXT: [[I10:%.*]] = load i16, i16* [[I9]], align 2
+; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i16, ptr [[ARG]], i64 [[I8]]
+; CHECK-NEXT: [[I10:%.*]] = load i16, ptr [[I9]], align 2
; CHECK-NEXT: [[I11:%.*]] = zext i16 [[I10]] to i32
; CHECK-NEXT: [[I12]] = sub nsw i32 [[I6]], [[I11]]
; CHECK-NEXT: [[I13:%.*]] = icmp ne i16 [[I10]], 0
@@ -186,7 +186,7 @@ define dso_local i32 @i32_loop_add_i16(i16* nocapture readonly %arg) {
; CHECK-NEXT: ret i32 [[I17]]
;
bb:
- %i = load i16, i16* %arg, align 2
+ %i = load i16, ptr %arg, align 2
%i1 = zext i16 %i to i32
%i2 = add i16 %i, -1
%i3 = icmp ult i16 %i2, 31
@@ -197,8 +197,8 @@ bb4: ; preds = %bb4, %bb
%i6 = phi i32 [ %i12, %bb4 ], [ %i1, %bb ]
%i7 = add i32 %i5, 1
%i8 = zext i32 %i7 to i64
- %i9 = getelementptr inbounds i16, i16* %arg, i64 %i8
- %i10 = load i16, i16* %i9, align 2
+ %i9 = getelementptr inbounds i16, ptr %arg, i64 %i8
+ %i10 = load i16, ptr %i9, align 2
%i11 = zext i16 %i10 to i32
%i12 = sub nsw i32 %i6, %i11
%i13 = icmp ne i16 %i10, 0
@@ -211,10 +211,10 @@ bb16: ; preds = %bb4, %bb
ret i32 %i17
}
-define dso_local i32 @i16_loop_add_i16(i16* nocapture readonly %arg) {
+define dso_local i32 @i16_loop_add_i16(ptr nocapture readonly %arg) {
; CHECK-LABEL: @i16_loop_add_i16(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = load i16, i16* [[ARG:%.*]], align 2
+; CHECK-NEXT: [[I:%.*]] = load i16, ptr [[ARG:%.*]], align 2
; CHECK-NEXT: [[I1:%.*]] = icmp ne i16 [[I]], 0
; CHECK-NEXT: [[I2:%.*]] = icmp slt i16 [[I]], 32
; CHECK-NEXT: [[I3:%.*]] = and i1 [[I1]], [[I2]]
@@ -224,8 +224,8 @@ define dso_local i32 @i16_loop_add_i16(i16* nocapture readonly %arg) {
; CHECK-NEXT: [[I6:%.*]] = phi i16 [ [[I11:%.*]], [[BB4]] ], [ [[I]], [[BB]] ]
; CHECK-NEXT: [[I7]] = add i32 [[I5]], 1
; CHECK-NEXT: [[I8:%.*]] = zext i32 [[I7]] to i64
-; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i16, i16* [[ARG]], i64 [[I8]]
-; CHECK-NEXT: [[I10:%.*]] = load i16, i16* [[I9]], align 2
+; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i16, ptr [[ARG]], i64 [[I8]]
+; CHECK-NEXT: [[I10:%.*]] = load i16, ptr [[I9]], align 2
; CHECK-NEXT: [[I11]] = sub i16 [[I6]], [[I10]]
; CHECK-NEXT: [[I12:%.*]] = icmp ne i16 [[I10]], 0
; CHECK-NEXT: [[I13:%.*]] = icmp slt i16 [[I11]], 32
@@ -237,7 +237,7 @@ define dso_local i32 @i16_loop_add_i16(i16* nocapture readonly %arg) {
; CHECK-NEXT: ret i32 [[I17]]
;
bb:
- %i = load i16, i16* %arg, align 2
+ %i = load i16, ptr %arg, align 2
%i1 = icmp ne i16 %i, 0
%i2 = icmp slt i16 %i, 32
%i3 = and i1 %i1, %i2
@@ -248,8 +248,8 @@ bb4: ; preds = %bb4, %bb
%i6 = phi i16 [ %i11, %bb4 ], [ %i, %bb ]
%i7 = add i32 %i5, 1
%i8 = zext i32 %i7 to i64
- %i9 = getelementptr inbounds i16, i16* %arg, i64 %i8
- %i10 = load i16, i16* %i9, align 2
+ %i9 = getelementptr inbounds i16, ptr %arg, i64 %i8
+ %i10 = load i16, ptr %i9, align 2
%i11 = sub i16 %i6, %i10
%i12 = icmp ne i16 %i10, 0
%i13 = icmp slt i16 %i11, 32
@@ -262,10 +262,10 @@ bb15: ; preds = %bb4, %bb
ret i32 %i17
}
-define dso_local i32 @i16_loop_sub_i16(i16* nocapture readonly %arg) {
+define dso_local i32 @i16_loop_sub_i16(ptr nocapture readonly %arg) {
; CHECK-LABEL: @i16_loop_sub_i16(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = load i16, i16* [[ARG:%.*]], align 2
+; CHECK-NEXT: [[I:%.*]] = load i16, ptr [[ARG:%.*]], align 2
; CHECK-NEXT: [[I1:%.*]] = icmp ne i16 [[I]], 0
; CHECK-NEXT: [[I2:%.*]] = icmp slt i16 [[I]], 32
; CHECK-NEXT: [[I3:%.*]] = and i1 [[I1]], [[I2]]
@@ -275,8 +275,8 @@ define dso_local i32 @i16_loop_sub_i16(i16* nocapture readonly %arg) {
; CHECK-NEXT: [[I6:%.*]] = phi i16 [ [[I11:%.*]], [[BB4]] ], [ [[I]], [[BB]] ]
; CHECK-NEXT: [[I7]] = add i32 [[I5]], 1
; CHECK-NEXT: [[I8:%.*]] = zext i32 [[I7]] to i64
-; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i16, i16* [[ARG]], i64 [[I8]]
-; CHECK-NEXT: [[I10:%.*]] = load i16, i16* [[I9]], align 2
+; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i16, ptr [[ARG]], i64 [[I8]]
+; CHECK-NEXT: [[I10:%.*]] = load i16, ptr [[I9]], align 2
; CHECK-NEXT: [[I11]] = sub i16 [[I6]], [[I10]]
; CHECK-NEXT: [[I12:%.*]] = icmp ne i16 [[I10]], 0
; CHECK-NEXT: [[I13:%.*]] = icmp slt i16 [[I11]], 32
@@ -288,7 +288,7 @@ define dso_local i32 @i16_loop_sub_i16(i16* nocapture readonly %arg) {
; CHECK-NEXT: ret i32 [[I17]]
;
bb:
- %i = load i16, i16* %arg, align 2
+ %i = load i16, ptr %arg, align 2
%i1 = icmp ne i16 %i, 0
%i2 = icmp slt i16 %i, 32
%i3 = and i1 %i1, %i2
@@ -299,8 +299,8 @@ bb4: ; preds = %bb4, %bb
%i6 = phi i16 [ %i11, %bb4 ], [ %i, %bb ]
%i7 = add i32 %i5, 1
%i8 = zext i32 %i7 to i64
- %i9 = getelementptr inbounds i16, i16* %arg, i64 %i8
- %i10 = load i16, i16* %i9, align 2
+ %i9 = getelementptr inbounds i16, ptr %arg, i64 %i8
+ %i10 = load i16, ptr %i9, align 2
%i11 = sub i16 %i6, %i10
%i12 = icmp ne i16 %i10, 0
%i13 = icmp slt i16 %i11, 32
@@ -313,10 +313,10 @@ bb15: ; preds = %bb4, %bb
ret i32 %i17
}
-define dso_local i32 @i32_loop_sub_i16(i16* nocapture readonly %arg) {
+define dso_local i32 @i32_loop_sub_i16(ptr nocapture readonly %arg) {
; CHECK-LABEL: @i32_loop_sub_i16(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = load i16, i16* [[ARG:%.*]], align 2
+; CHECK-NEXT: [[I:%.*]] = load i16, ptr [[ARG:%.*]], align 2
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[I]] to i32
; CHECK-NEXT: [[I1:%.*]] = zext i16 [[I]] to i32
; CHECK-NEXT: [[I2:%.*]] = add i32 [[TMP0]], -1
@@ -327,8 +327,8 @@ define dso_local i32 @i32_loop_sub_i16(i16* nocapture readonly %arg) {
; CHECK-NEXT: [[I6:%.*]] = phi i32 [ [[I12:%.*]], [[BB4]] ], [ [[I1]], [[BB]] ]
; CHECK-NEXT: [[I7]] = add i32 [[I5]], 1
; CHECK-NEXT: [[I8:%.*]] = zext i32 [[I7]] to i64
-; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i16, i16* [[ARG]], i64 [[I8]]
-; CHECK-NEXT: [[I10:%.*]] = load i16, i16* [[I9]], align 2
+; CHECK-NEXT: [[I9:%.*]] = getelementptr inbounds i16, ptr [[ARG]], i64 [[I8]]
+; CHECK-NEXT: [[I10:%.*]] = load i16, ptr [[I9]], align 2
; CHECK-NEXT: [[I11:%.*]] = zext i16 [[I10]] to i32
; CHECK-NEXT: [[I12]] = sub nsw i32 [[I6]], [[I11]]
; CHECK-NEXT: [[I13:%.*]] = icmp ne i16 [[I10]], 0
@@ -340,7 +340,7 @@ define dso_local i32 @i32_loop_sub_i16(i16* nocapture readonly %arg) {
; CHECK-NEXT: ret i32 [[I17]]
;
bb:
- %i = load i16, i16* %arg, align 2
+ %i = load i16, ptr %arg, align 2
%i1 = zext i16 %i to i32
%i2 = add i16 %i, -1
%i3 = icmp ult i16 %i2, 31
@@ -351,8 +351,8 @@ bb4: ; preds = %bb4, %bb
%i6 = phi i32 [ %i12, %bb4 ], [ %i1, %bb ]
%i7 = add i32 %i5, 1
%i8 = zext i32 %i7 to i64
- %i9 = getelementptr inbounds i16, i16* %arg, i64 %i8
- %i10 = load i16, i16* %i9, align 2
+ %i9 = getelementptr inbounds i16, ptr %arg, i64 %i8
+ %i10 = load i16, ptr %i9, align 2
%i11 = zext i16 %i10 to i32
%i12 = sub nsw i32 %i6, %i11
%i13 = icmp ne i16 %i10, 0
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll b/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
index 96389f206f01d..3859ee82e03d5 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
@@ -3,10 +3,10 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-define dso_local i32 @avoid_trunc_gep(i8* nocapture readonly %ip) {
+define dso_local i32 @avoid_trunc_gep(ptr nocapture readonly %ip) {
; CHECK-LABEL: @avoid_trunc_gep(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TAG_0_IN8:%.*]] = load i8, i8* [[IP:%.*]], align 1
+; CHECK-NEXT: [[TAG_0_IN8:%.*]] = load i8, ptr [[IP:%.*]], align 1
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[TAG_0_IN8]] to i32
; CHECK-NEXT: [[CMP9:%.*]] = icmp ult i32 [[TMP0]], 100
; CHECK-NEXT: br i1 [[CMP9]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]]
@@ -15,8 +15,8 @@ define dso_local i32 @avoid_trunc_gep(i8* nocapture readonly %ip) {
; CHECK: for.body:
; CHECK-NEXT: [[TAG_0_IN10:%.*]] = phi i32 [ [[TMP1:%.*]], [[FOR_BODY]] ], [ [[TMP0]], [[FOR_BODY_PREHEADER]] ]
; CHECK-NEXT: [[TAG_0:%.*]] = zext i32 [[TAG_0_IN10]] to i64
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, i8* [[IP]], i64 [[TAG_0]]
-; CHECK-NEXT: [[TAG_0_IN:%.*]] = load i8, i8* [[ARRAYIDX]], align 1
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[IP]], i64 [[TAG_0]]
+; CHECK-NEXT: [[TAG_0_IN:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
; CHECK-NEXT: [[TMP1]] = zext i8 [[TAG_0_IN]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP1]], 100
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END_LOOPEXIT:%.*]]
@@ -27,7 +27,7 @@ define dso_local i32 @avoid_trunc_gep(i8* nocapture readonly %ip) {
; CHECK-NEXT: ret i32 [[TAG_0_IN_LCSSA]]
;
entry:
- %tag.0.in8 = load i8, i8* %ip, align 1
+ %tag.0.in8 = load i8, ptr %ip, align 1
%cmp9 = icmp ult i8 %tag.0.in8, 100
br i1 %cmp9, label %for.body.preheader, label %for.end
@@ -37,8 +37,8 @@ for.body.preheader: ; preds = %entry
for.body: ; preds = %for.body.preheader, %for.body
%tag.0.in10 = phi i8 [ %tag.0.in, %for.body ], [ %tag.0.in8, %for.body.preheader ]
%tag.0 = zext i8 %tag.0.in10 to i64
- %arrayidx = getelementptr inbounds i8, i8* %ip, i64 %tag.0
- %tag.0.in = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %ip, i64 %tag.0
+ %tag.0.in = load i8, ptr %arrayidx, align 1
%cmp = icmp ult i8 %tag.0.in, 100
br i1 %cmp, label %for.body, label %for.end.loopexit
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll b/llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll
index 320e9bc5e5431..8c539c7341467 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll
@@ -4,28 +4,27 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
%struct.bar = type { %struct.foo }
-%struct.foo = type { %struct.wobble* }
-%struct.wobble = type { %struct.zot* }
-%struct.zot = type <{ %struct.wobble, %struct.zot*, %struct.wobble*, i8, [7 x i8] }>
+%struct.foo = type { ptr }
+%struct.wobble = type { ptr }
+%struct.zot = type <{ %struct.wobble, ptr, ptr, i8, [7 x i8] }>
@global = external global %struct.bar, align 8
define i64 @zext_trunc_i8_i16_i32_i64() {
; CHECK-LABEL: @zext_trunc_i8_i16_i32_i64(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAR:%.*]] = load %struct.wobble*, %struct.wobble** getelementptr inbounds ([[STRUCT_BAR:%.*]], %struct.bar* @global, i64 0, i32 0, i32 0), align 8
+; CHECK-NEXT: [[VAR:%.*]] = load ptr, ptr @global, align 8
; CHECK-NEXT: br label [[PREHEADER:%.*]]
; CHECK: preheader:
; CHECK-NEXT: br label [[HEADER:%.*]]
; CHECK: header:
; CHECK-NEXT: [[VAR4:%.*]] = phi i64 [ [[VAR30:%.*]], [[LATCH:%.*]] ], [ 0, [[PREHEADER]] ]
-; CHECK-NEXT: [[VAR5:%.*]] = phi %struct.wobble* [ [[VAR38:%.*]], [[LATCH]] ], [ [[VAR]], [[PREHEADER]] ]
+; CHECK-NEXT: [[VAR5:%.*]] = phi ptr [ [[VAR38:%.*]], [[LATCH]] ], [ [[VAR]], [[PREHEADER]] ]
; CHECK-NEXT: [[VAR6:%.*]] = phi i32 [ [[VAR21:%.*]], [[LATCH]] ], [ 0, [[PREHEADER]] ]
; CHECK-NEXT: br label [[MIDBLOCK:%.*]]
; CHECK: midblock:
-; CHECK-NEXT: [[VAR15:%.*]] = getelementptr inbounds [[STRUCT_WOBBLE:%.*]], %struct.wobble* [[VAR5]], i64 9
-; CHECK-NEXT: [[VAR16:%.*]] = bitcast %struct.wobble* [[VAR15]] to i16*
-; CHECK-NEXT: [[VAR17:%.*]] = load i16, i16* [[VAR16]], align 8
+; CHECK-NEXT: [[VAR15:%.*]] = getelementptr inbounds [[STRUCT_WOBBLE:%.*]], ptr [[VAR5]], i64 9
+; CHECK-NEXT: [[VAR17:%.*]] = load i16, ptr [[VAR15]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[VAR17]] to i32
; CHECK-NEXT: [[VAR18:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK-NEXT: [[VAR19:%.*]] = lshr i32 [[TMP0]], 8
@@ -41,17 +40,17 @@ define i64 @zext_trunc_i8_i16_i32_i64() {
; CHECK-NEXT: [[VAR30]] = or i64 [[VAR29]], [[VAR27]]
; CHECK-NEXT: br label [[LATCH]]
; CHECK: latch:
-; CHECK-NEXT: [[VAR34:%.*]] = getelementptr inbounds [[STRUCT_WOBBLE]], %struct.wobble* [[VAR5]], i64 1, i32 0
-; CHECK-NEXT: [[VAR35:%.*]] = load %struct.zot*, %struct.zot** [[VAR34]], align 8
-; CHECK-NEXT: [[VAR36:%.*]] = icmp eq %struct.zot* [[VAR35]], null
-; CHECK-NEXT: [[VAR37:%.*]] = getelementptr inbounds [[STRUCT_ZOT:%.*]], %struct.zot* [[VAR35]], i64 0, i32 2
-; CHECK-NEXT: [[VAR38]] = load %struct.wobble*, %struct.wobble** [[VAR37]], align 8
+; CHECK-NEXT: [[VAR34:%.*]] = getelementptr inbounds [[STRUCT_WOBBLE]], ptr [[VAR5]], i64 1, i32 0
+; CHECK-NEXT: [[VAR35:%.*]] = load ptr, ptr [[VAR34]], align 8
+; CHECK-NEXT: [[VAR36:%.*]] = icmp eq ptr [[VAR35]], null
+; CHECK-NEXT: [[VAR37:%.*]] = getelementptr inbounds [[STRUCT_ZOT:%.*]], ptr [[VAR35]], i64 0, i32 2
+; CHECK-NEXT: [[VAR38]] = load ptr, ptr [[VAR37]], align 8
; CHECK-NEXT: br i1 [[VAR36]], label [[EXIT:%.*]], label [[HEADER]]
; CHECK: exit:
; CHECK-NEXT: ret i64 [[VAR30]]
;
entry:
- %var = load %struct.wobble*, %struct.wobble** getelementptr inbounds (%struct.bar, %struct.bar* @global, i64 0, i32 0, i32 0), align 8
+ %var = load ptr, ptr @global, align 8
br label %preheader
preheader:
@@ -59,14 +58,13 @@ preheader:
header: ; preds = %bb63, %bb
%var4 = phi i64 [ %var30, %latch ], [ 0, %preheader ]
- %var5 = phi %struct.wobble* [ %var38, %latch ], [ %var, %preheader ]
+ %var5 = phi ptr [ %var38, %latch ], [ %var, %preheader ]
%var6 = phi i8 [ %var21, %latch ], [ 0, %preheader ]
br label %midblock
midblock: ; preds = %bb9
- %var15 = getelementptr inbounds %struct.wobble, %struct.wobble* %var5, i64 9
- %var16 = bitcast %struct.wobble* %var15 to i16*
- %var17 = load i16, i16* %var16, align 8
+ %var15 = getelementptr inbounds %struct.wobble, ptr %var5, i64 9
+ %var17 = load i16, ptr %var15, align 8
%var18 = icmp eq i16 %var17, 0
%var19 = lshr i16 %var17, 8
%var20 = trunc i16 %var19 to i8
@@ -83,11 +81,11 @@ midblock: ; preds = %bb9
br label %latch
latch: ; preds = %bb14, %bb9
- %var34 = getelementptr inbounds %struct.wobble, %struct.wobble* %var5, i64 1, i32 0
- %var35 = load %struct.zot*, %struct.zot** %var34, align 8
- %var36 = icmp eq %struct.zot* %var35, null
- %var37 = getelementptr inbounds %struct.zot, %struct.zot* %var35, i64 0, i32 2
- %var38 = load %struct.wobble*, %struct.wobble** %var37, align 8
+ %var34 = getelementptr inbounds %struct.wobble, ptr %var5, i64 1, i32 0
+ %var35 = load ptr, ptr %var34, align 8
+ %var36 = icmp eq ptr %var35, null
+ %var37 = getelementptr inbounds %struct.zot, ptr %var35, i64 0, i32 2
+ %var38 = load ptr, ptr %var37, align 8
br i1 %var36, label %exit, label %header
exit:
@@ -97,19 +95,18 @@ exit:
define i64 @with_undef() {
; CHECK-LABEL: @with_undef(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAR:%.*]] = load %struct.wobble*, %struct.wobble** getelementptr inbounds ([[STRUCT_BAR:%.*]], %struct.bar* @global, i64 0, i32 0, i32 0), align 8
+; CHECK-NEXT: [[VAR:%.*]] = load ptr, ptr @global, align 8
; CHECK-NEXT: br label [[PREHEADER:%.*]]
; CHECK: preheader:
; CHECK-NEXT: br label [[HEADER:%.*]]
; CHECK: header:
; CHECK-NEXT: [[VAR4:%.*]] = phi i64 [ [[VAR30:%.*]], [[LATCH:%.*]] ], [ undef, [[PREHEADER]] ]
-; CHECK-NEXT: [[VAR5:%.*]] = phi %struct.wobble* [ [[VAR38:%.*]], [[LATCH]] ], [ [[VAR]], [[PREHEADER]] ]
+; CHECK-NEXT: [[VAR5:%.*]] = phi ptr [ [[VAR38:%.*]], [[LATCH]] ], [ [[VAR]], [[PREHEADER]] ]
; CHECK-NEXT: [[VAR6:%.*]] = phi i32 [ [[VAR21:%.*]], [[LATCH]] ], [ 0, [[PREHEADER]] ]
; CHECK-NEXT: br label [[MIDBLOCK:%.*]]
; CHECK: midblock:
-; CHECK-NEXT: [[VAR15:%.*]] = getelementptr inbounds [[STRUCT_WOBBLE:%.*]], %struct.wobble* [[VAR5]], i64 9
-; CHECK-NEXT: [[VAR16:%.*]] = bitcast %struct.wobble* [[VAR15]] to i16*
-; CHECK-NEXT: [[VAR17:%.*]] = load i16, i16* [[VAR16]], align 8
+; CHECK-NEXT: [[VAR15:%.*]] = getelementptr inbounds [[STRUCT_WOBBLE:%.*]], ptr [[VAR5]], i64 9
+; CHECK-NEXT: [[VAR17:%.*]] = load i16, ptr [[VAR15]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[VAR17]] to i32
; CHECK-NEXT: [[VAR18:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK-NEXT: [[VAR19:%.*]] = lshr i32 [[TMP0]], 8
@@ -125,17 +122,17 @@ define i64 @with_undef() {
; CHECK-NEXT: [[VAR30]] = or i64 [[VAR29]], [[VAR27]]
; CHECK-NEXT: br label [[LATCH]]
; CHECK: latch:
-; CHECK-NEXT: [[VAR34:%.*]] = getelementptr inbounds [[STRUCT_WOBBLE]], %struct.wobble* [[VAR5]], i64 1, i32 0
-; CHECK-NEXT: [[VAR35:%.*]] = load %struct.zot*, %struct.zot** [[VAR34]], align 8
-; CHECK-NEXT: [[VAR36:%.*]] = icmp eq %struct.zot* [[VAR35]], null
-; CHECK-NEXT: [[VAR37:%.*]] = getelementptr inbounds [[STRUCT_ZOT:%.*]], %struct.zot* [[VAR35]], i64 0, i32 2
-; CHECK-NEXT: [[VAR38]] = load %struct.wobble*, %struct.wobble** [[VAR37]], align 8
+; CHECK-NEXT: [[VAR34:%.*]] = getelementptr inbounds [[STRUCT_WOBBLE]], ptr [[VAR5]], i64 1, i32 0
+; CHECK-NEXT: [[VAR35:%.*]] = load ptr, ptr [[VAR34]], align 8
+; CHECK-NEXT: [[VAR36:%.*]] = icmp eq ptr [[VAR35]], null
+; CHECK-NEXT: [[VAR37:%.*]] = getelementptr inbounds [[STRUCT_ZOT:%.*]], ptr [[VAR35]], i64 0, i32 2
+; CHECK-NEXT: [[VAR38]] = load ptr, ptr [[VAR37]], align 8
; CHECK-NEXT: br i1 [[VAR36]], label [[EXIT:%.*]], label [[HEADER]]
; CHECK: exit:
; CHECK-NEXT: ret i64 [[VAR30]]
;
entry:
- %var = load %struct.wobble*, %struct.wobble** getelementptr inbounds (%struct.bar, %struct.bar* @global, i64 0, i32 0, i32 0), align 8
+ %var = load ptr, ptr @global, align 8
br label %preheader
preheader:
@@ -143,14 +140,13 @@ preheader:
header: ; preds = %bb63, %bb
%var4 = phi i64 [ %var30, %latch ], [ undef, %preheader ]
- %var5 = phi %struct.wobble* [ %var38, %latch ], [ %var, %preheader ]
+ %var5 = phi ptr [ %var38, %latch ], [ %var, %preheader ]
%var6 = phi i8 [ %var21, %latch ], [ undef, %preheader ]
br label %midblock
midblock: ; preds = %bb9
- %var15 = getelementptr inbounds %struct.wobble, %struct.wobble* %var5, i64 9
- %var16 = bitcast %struct.wobble* %var15 to i16*
- %var17 = load i16, i16* %var16, align 8
+ %var15 = getelementptr inbounds %struct.wobble, ptr %var5, i64 9
+ %var17 = load i16, ptr %var15, align 8
%var18 = icmp eq i16 %var17, 0
%var19 = lshr i16 %var17, 8
%var20 = trunc i16 %var19 to i8
@@ -167,11 +163,11 @@ midblock: ; preds = %bb9
br label %latch
latch: ; preds = %bb14, %bb9
- %var34 = getelementptr inbounds %struct.wobble, %struct.wobble* %var5, i64 1, i32 0
- %var35 = load %struct.zot*, %struct.zot** %var34, align 8
- %var36 = icmp eq %struct.zot* %var35, null
- %var37 = getelementptr inbounds %struct.zot, %struct.zot* %var35, i64 0, i32 2
- %var38 = load %struct.wobble*, %struct.wobble** %var37, align 8
+ %var34 = getelementptr inbounds %struct.wobble, ptr %var5, i64 1, i32 0
+ %var35 = load ptr, ptr %var34, align 8
+ %var36 = icmp eq ptr %var35, null
+ %var37 = getelementptr inbounds %struct.zot, ptr %var35, i64 0, i32 2
+ %var38 = load ptr, ptr %var37, align 8
br i1 %var36, label %exit, label %header
exit:
diff --git a/llvm/test/Transforms/TypePromotion/ARM/calls.ll b/llvm/test/Transforms/TypePromotion/ARM/calls.ll
index 73efebda4a0ca..b626dcaf9bf54 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/calls.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/calls.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
-define i8 @call_with_imms(i8* %arg) {
+define i8 @call_with_imms(ptr %arg) {
; CHECK-LABEL: @call_with_imms(
-; CHECK-NEXT: [[CALL:%.*]] = tail call arm_aapcs_vfpcc zeroext i8 @dummy2(i8* nonnull [[ARG:%.*]], i8 zeroext 0, i8 zeroext 0)
+; CHECK-NEXT: [[CALL:%.*]] = tail call arm_aapcs_vfpcc zeroext i8 @dummy2(ptr nonnull [[ARG:%.*]], i8 zeroext 0, i8 zeroext 0)
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[CALL]], 0
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i8 [[CALL]], i8 1
; CHECK-NEXT: ret i8 [[RES]]
;
- %call = tail call arm_aapcs_vfpcc zeroext i8 @dummy2(i8* nonnull %arg, i8 zeroext 0, i8 zeroext 0)
+ %call = tail call arm_aapcs_vfpcc zeroext i8 @dummy2(ptr nonnull %arg, i8 zeroext 0, i8 zeroext 0)
%cmp = icmp eq i8 %call, 0
%res = select i1 %cmp, i8 %call, i8 1
ret i8 %res
@@ -79,49 +79,49 @@ define i16 @promote_i8_sink_i16_2(i8 zeroext %arg0, i8 zeroext %arg1, i16 zeroex
define void @zext_i64() {
; CHECK-LABEL: @zext_i64(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @uc, align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr @uc, align 1
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i64
-; CHECK-NEXT: store i64 [[CONV]], i64* @LL, align 8
+; CHECK-NEXT: store i64 [[CONV]], ptr @LL, align 8
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], 42
; CHECK-NEXT: [[CONV1:%.*]] = zext i1 [[CMP]] to i32
-; CHECK-NEXT: [[CALL:%.*]] = tail call i32 bitcast (i32 (...)* @assert to i32 (i32)*)(i32 [[CONV1]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @assert(i32 [[CONV1]])
; CHECK-NEXT: ret void
;
entry:
- %0 = load i8, i8* @uc, align 1
+ %0 = load i8, ptr @uc, align 1
%conv = zext i8 %0 to i64
- store i64 %conv, i64* @LL, align 8
+ store i64 %conv, ptr @LL, align 8
%cmp = icmp eq i8 %0, 42
%conv1 = zext i1 %cmp to i32
- %call = tail call i32 bitcast (i32 (...)* @assert to i32 (i32)*)(i32 %conv1)
+ %call = tail call i32 @assert(i32 %conv1)
ret void
}
- at a = global i16* null, align 4
+ at a = global ptr null, align 4
@b = global i32 0, align 4
define i32 @constexpr() {
; CHECK-LABEL: @constexpr(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store i32 ptrtoint (i32* @b to i32), i32* @b, align 4
-; CHECK-NEXT: [[TMP0:%.*]] = load i16*, i16** @a, align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
-; CHECK-NEXT: [[OR:%.*]] = or i16 [[TMP1]], ptrtoint (i32* @b to i16)
-; CHECK-NEXT: store i16 [[OR]], i16* [[TMP0]], align 2
+; CHECK-NEXT: store i32 ptrtoint (ptr @b to i32), ptr @b, align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr @a, align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
+; CHECK-NEXT: [[OR:%.*]] = or i16 [[TMP1]], ptrtoint (ptr @b to i16)
+; CHECK-NEXT: store i16 [[OR]], ptr [[TMP0]], align 2
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i16 [[OR]], 4
; CHECK-NEXT: [[CONV3:%.*]] = zext i1 [[CMP]] to i32
-; CHECK-NEXT: [[CALL:%.*]] = tail call i32 bitcast (i32 (...)* @e to i32 (i32)*)(i32 [[CONV3]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @e(i32 [[CONV3]])
; CHECK-NEXT: ret i32 undef
;
entry:
- store i32 ptrtoint (i32* @b to i32), i32* @b, align 4
- %0 = load i16*, i16** @a, align 4
- %1 = load i16, i16* %0, align 2
- %or = or i16 %1, ptrtoint (i32* @b to i16)
- store i16 %or, i16* %0, align 2
+ store i32 ptrtoint (ptr @b to i32), ptr @b, align 4
+ %0 = load ptr, ptr @a, align 4
+ %1 = load i16, ptr %0, align 2
+ %or = or i16 %1, ptrtoint (ptr @b to i16)
+ store i16 %or, ptr %0, align 2
%cmp = icmp ne i16 %or, 4
%conv3 = zext i1 %cmp to i32
- %call = tail call i32 bitcast (i32 (...)* @e to i32 (i32)*)(i32 %conv3) #2
+ %call = tail call i32 @e(i32 %conv3) #2
ret i32 undef
}
@@ -168,8 +168,8 @@ define hidden i32 @call_return_pointer(i8 zeroext %p_13) local_unnamed_addr #0 {
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[P_13:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
; CHECK-NEXT: [[CONV1:%.*]] = zext i8 [[TMP1]] to i16
-; CHECK-NEXT: [[CALL:%.*]] = tail call i16** @func_62(i8 zeroext undef, i32 undef, i16 signext [[CONV1]], i32* undef)
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_ANON:%.*]], %struct.anon* @g_893, i32 0, i32 0), align 4
+; CHECK-NEXT: [[CALL:%.*]] = tail call ptr @func_62(i8 zeroext undef, i32 undef, i16 signext [[CONV1]], ptr undef)
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @g_893, align 4
; CHECK-NEXT: [[CONV2:%.*]] = trunc i32 [[TMP2]] to i16
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
@@ -187,8 +187,8 @@ define hidden i32 @call_return_pointer(i8 zeroext %p_13) local_unnamed_addr #0 {
;
entry:
%conv1 = zext i8 %p_13 to i16
- %call = tail call i16** @func_62(i8 zeroext undef, i32 undef, i16 signext %conv1, i32* undef)
- %0 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @g_893, i32 0, i32 0), align 4
+ %call = tail call ptr @func_62(i8 zeroext undef, i32 undef, i16 signext %conv1, ptr undef)
+ %0 = load i32, ptr @g_893, align 4
%conv2 = trunc i32 %0 to i16
br label %for.cond
@@ -219,7 +219,7 @@ define i32 @check_zext_phi_call_arg() {
; CHECK-NEXT: [[D_SROA_0_0_BE]] = phi i32 [ [[TMP0:%.*]], [[IF_THEN]] ], [ 0, [[FOR_COND]] ]
; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: if.then:
-; CHECK-NEXT: [[CALL:%.*]] = tail call zeroext i16 bitcast (i16 (...)* @f to i16 (i32)*)(i32 [[D_SROA_0_0]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call zeroext i16 @f(i32 [[D_SROA_0_0]])
; CHECK-NEXT: [[TMP0]] = zext i16 [[CALL]] to i32
; CHECK-NEXT: br label [[FOR_COND_BACKEDGE]]
;
@@ -237,37 +237,35 @@ for.cond.backedge: ; preds = %for.cond, %if.then
if.then: ; preds = %for.cond
%d.sroa.0.0.insert.ext = zext i16 %d.sroa.0.0 to i32
- %call = tail call zeroext i16 bitcast (i16 (...)* @f to i16 (i32)*)(i32 %d.sroa.0.0.insert.ext) #2
+ %call = tail call zeroext i16 @f(i32 %d.sroa.0.0.insert.ext) #2
br label %for.cond.backedge
}
%struct.atomic_flag = type { i8 }
-define zeroext i1 @atomic_flag_test_and_set(%struct.atomic_flag* %object) {
+define zeroext i1 @atomic_flag_test_and_set(ptr %object) {
; CHECK-LABEL: @atomic_flag_test_and_set(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[_VALUE:%.*]] = getelementptr inbounds [[STRUCT_ATOMIC_FLAG:%.*]], %struct.atomic_flag* [[OBJECT:%.*]], i32 0, i32 0
-; CHECK-NEXT: [[CALL:%.*]] = tail call arm_aapcscc zeroext i8 @__atomic_exchange_1(i8* [[_VALUE]], i8 zeroext 1, i32 5)
+; CHECK-NEXT: [[CALL:%.*]] = tail call arm_aapcscc zeroext i8 @__atomic_exchange_1(ptr [[OBJECT:%.*]], i8 zeroext 1, i32 5)
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[CALL]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[TOBOOL]]
;
entry:
- %_Value = getelementptr inbounds %struct.atomic_flag, %struct.atomic_flag* %object, i32 0, i32 0
- %call = tail call arm_aapcscc zeroext i8 @__atomic_exchange_1(i8* %_Value, i8 zeroext 1, i32 5) #1
+ %call = tail call arm_aapcscc zeroext i8 @__atomic_exchange_1(ptr %object, i8 zeroext 1, i32 5) #1
%0 = and i8 %call, 1
%tobool = icmp ne i8 %0, 0
ret i1 %tobool
}
-define i1 @i1_zeroext_call(i16* %ts, i32 %a, i16* %b, i8* %c) {
+define i1 @i1_zeroext_call(ptr %ts, i32 %a, ptr %b, ptr %c) {
; CHECK-LABEL: @i1_zeroext_call(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[TS:%.*]], align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[TS:%.*]], align 2
; CHECK-NEXT: [[CONV_I860:%.*]] = trunc i32 [[A:%.*]] to i16
-; CHECK-NEXT: store i16 [[CONV_I860]], i16* [[B:%.*]], align 2
-; CHECK-NEXT: [[CALL_I848:%.*]] = call zeroext i1 @i1_zeroext(i8* [[C:%.*]], i32 64, i16 zeroext [[CONV_I860]])
+; CHECK-NEXT: store i16 [[CONV_I860]], ptr [[B:%.*]], align 2
+; CHECK-NEXT: [[CALL_I848:%.*]] = call zeroext i1 @i1_zeroext(ptr [[C:%.*]], i32 64, i16 zeroext [[CONV_I860]])
; CHECK-NEXT: br i1 [[CALL_I848]], label [[IF_THEN223:%.*]], label [[IF_ELSE227:%.*]]
; CHECK: if.then223:
; CHECK-NEXT: [[CMP235:%.*]] = icmp eq i16 [[TMP0]], [[CONV_I860]]
@@ -280,10 +278,10 @@ define i1 @i1_zeroext_call(i16* %ts, i32 %a, i16* %b, i8* %c) {
; CHECK-NEXT: ret i1 [[RETVAL]]
;
entry:
- %0 = load i16, i16* %ts, align 2
+ %0 = load i16, ptr %ts, align 2
%conv.i860 = trunc i32 %a to i16
- store i16 %conv.i860, i16* %b, align 2
- %call.i848 = call zeroext i1 @i1_zeroext(i8* %c, i32 64, i16 zeroext %conv.i860)
+ store i16 %conv.i860, ptr %b, align 2
+ %call.i848 = call zeroext i1 @i1_zeroext(ptr %c, i32 64, i16 zeroext %conv.i860)
br i1 %call.i848, label %if.then223, label %if.else227
if.then223:
@@ -325,17 +323,17 @@ define i16 @promote_arg_pass_to_call(i16 zeroext %arg1, i16 zeroext %arg2) {
declare i32 @assert(...)
declare i8 @dummy_i8(i8)
-declare i8 @dummy2(i8*, i8, i8)
+declare i8 @dummy2(ptr, i8, i8)
declare i16 @dummy3(i16)
declare i16 @dummy4(i1, i8, i16)
declare dso_local i32 @e(...) local_unnamed_addr #1
declare dso_local zeroext i16 @f(...) local_unnamed_addr #1
-declare dso_local arm_aapcscc i8 @__atomic_exchange_1(i8*, i8, i32) local_unnamed_addr
+declare dso_local arm_aapcscc i8 @__atomic_exchange_1(ptr, i8, i32) local_unnamed_addr
-declare noalias i16** @func_62(i8 zeroext %p_63, i32 %p_64, i16 signext %p_65, i32* nocapture readnone %p_66)
+declare noalias ptr @func_62(i8 zeroext %p_63, i32 %p_64, i16 signext %p_65, ptr nocapture readnone %p_66)
declare fastcc signext i16 @safe_sub_func_int16_t_s_s(i16 signext %si2)
declare dso_local fastcc i64 @safe_sub_func_int64_t_s_s(i64, i64)
declare dso_local fastcc zeroext i8 @safe_lshift_func(i8 zeroext, i32)
declare dso_local fastcc zeroext i8 @safe_mul_func_uint8_t_u_u(i8 returned zeroext)
-declare i1 @i1_zeroext(i8*, i32, i16 zeroext)
+declare i1 @i1_zeroext(ptr, i32, i16 zeroext)
diff --git a/llvm/test/Transforms/TypePromotion/ARM/casts.ll b/llvm/test/Transforms/TypePromotion/ARM/casts.ll
index 80a4e178a34ca..3f0e545bda6ea 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/casts.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/casts.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
-define i16 @dsp_trunc(i32 %arg0, i32 %arg1, i16* %gep0, i16* %gep1) {
+define i16 @dsp_trunc(i32 %arg0, i32 %arg1, ptr %gep0, ptr %gep1) {
; CHECK-LABEL: @dsp_trunc(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ADD0:%.*]] = add i32 [[ARG0:%.*]], [[ARG1:%.*]]
; CHECK-NEXT: [[CONV0:%.*]] = trunc i32 [[ADD0]] to i16
; CHECK-NEXT: [[SUB0:%.*]] = sub i16 0, [[CONV0]]
-; CHECK-NEXT: [[LOAD0:%.*]] = load i16, i16* [[GEP0:%.*]], align 2
-; CHECK-NEXT: [[LOAD1:%.*]] = load i16, i16* [[GEP1:%.*]], align 2
+; CHECK-NEXT: [[LOAD0:%.*]] = load i16, ptr [[GEP0:%.*]], align 2
+; CHECK-NEXT: [[LOAD1:%.*]] = load i16, ptr [[GEP1:%.*]], align 2
; CHECK-NEXT: [[SUB1:%.*]] = sub i16 [[LOAD0]], [[SUB0]]
; CHECK-NEXT: [[ADD1:%.*]] = add i16 [[LOAD1]], [[SUB0]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i16 [[SUB1]], [[ADD1]]
@@ -19,8 +19,8 @@ entry:
%add0 = add i32 %arg0, %arg1
%conv0 = trunc i32 %add0 to i16
%sub0 = sub i16 0, %conv0
- %load0 = load i16, i16* %gep0, align 2
- %load1 = load i16, i16* %gep1, align 2
+ %load0 = load i16, ptr %gep0, align 2
+ %load1 = load i16, ptr %gep1, align 2
%sub1 = sub i16 %load0, %sub0
%add1 = add i16 %load1, %sub0
%cmp = icmp ult i16 %sub1, %add1
@@ -28,11 +28,11 @@ entry:
ret i16 %res
}
-define i8 @trunc_i16_i8(i16* %ptr, i16 zeroext %arg0, i8 zeroext %arg1) {
+define i8 @trunc_i16_i8(ptr %ptr, i16 zeroext %arg0, i8 zeroext %arg1) {
; CHECK-LABEL: @trunc_i16_i8(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* [[PTR:%.*]], align 2
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[PTR:%.*]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = add i16 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = trunc i16 [[TMP2]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
@@ -42,7 +42,7 @@ define i8 @trunc_i16_i8(i16* %ptr, i16 zeroext %arg0, i8 zeroext %arg1) {
; CHECK-NEXT: ret i8 [[TMP7]]
;
entry:
- %0 = load i16, i16* %ptr
+ %0 = load i16, ptr %ptr
%1 = add i16 %0, %arg0
%2 = trunc i16 %1 to i8
%3 = icmp ugt i8 %2, %arg1
@@ -51,11 +51,10 @@ entry:
}
; The pass perform the transform.
-define i8 @icmp_i32_zext(i8* %ptr) {
+define i8 @icmp_i32_zext(ptr %ptr) {
; CHECK-LABEL: @icmp_i32_zext(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, i8* [[PTR:%.*]], i32 0
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[GEP]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = sub nuw nsw i32 [[TMP1]], 1
; CHECK-NEXT: [[CONV44:%.*]] = zext i8 [[TMP0]] to i32
@@ -69,8 +68,8 @@ define i8 @icmp_i32_zext(i8* %ptr) {
; CHECK-NEXT: br i1 [[CMP52267]], label [[IF_END]], label [[EXIT:%.*]]
; CHECK: if.end:
; CHECK-NEXT: [[INC]] = add i32 [[SI_0274]], 1
-; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, i8* [[PTR]], i32 [[INC]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i8, i8* [[GEP1]], align 1
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 [[INC]]
+; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[GEP1]], align 1
; CHECK-NEXT: [[TMP5]] = zext i8 [[TMP4]] to i32
; CHECK-NEXT: br label [[BODY]]
; CHECK: exit:
@@ -78,8 +77,7 @@ define i8 @icmp_i32_zext(i8* %ptr) {
; CHECK-NEXT: ret i8 [[TMP6]]
;
entry:
- %gep = getelementptr inbounds i8, i8* %ptr, i32 0
- %0 = load i8, i8* %gep, align 1
+ %0 = load i8, ptr %ptr, align 1
%1 = sub nuw nsw i8 %0, 1
%conv44 = zext i8 %0 to i32
br label %preheader
@@ -96,8 +94,8 @@ body:
if.end:
%inc = add i32 %si.0274, 1
- %gep1 = getelementptr inbounds i8, i8* %ptr, i32 %inc
- %3 = load i8, i8* %gep1, align 1
+ %gep1 = getelementptr inbounds i8, ptr %ptr, i32 %inc
+ %3 = load i8, ptr %gep1, align 1
br label %body
exit:
@@ -108,32 +106,32 @@ exit:
define i32 @icmp_sext_zext_store_i8_i16() {
; CHECK-LABEL: @icmp_sext_zext_store_i8_i16(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* getelementptr inbounds ([16 x i8], [16 x i8]* @d_uch, i32 0, i32 2), align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr getelementptr inbounds ([16 x i8], ptr @d_uch, i32 0, i32 2), align 1
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i16
-; CHECK-NEXT: store i16 [[CONV]], i16* @sh1, align 2
+; CHECK-NEXT: store i16 [[CONV]], ptr @sh1, align 2
; CHECK-NEXT: [[CONV1:%.*]] = zext i8 [[TMP0]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @d_sh, i32 0, i32 2), align 2
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr inbounds ([16 x i16], ptr @d_sh, i32 0, i32 2), align 2
; CHECK-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CONV1]], [[CONV2]]
; CHECK-NEXT: [[CONV3:%.*]] = zext i1 [[CMP]] to i32
; CHECK-NEXT: ret i32 [[CONV3]]
;
entry:
- %0 = load i8, i8* getelementptr inbounds ([16 x i8], [16 x i8]* @d_uch, i32 0, i32 2), align 1
+ %0 = load i8, ptr getelementptr inbounds ([16 x i8], ptr @d_uch, i32 0, i32 2), align 1
%conv = zext i8 %0 to i16
- store i16 %conv, i16* @sh1, align 2
+ store i16 %conv, ptr @sh1, align 2
%conv1 = zext i8 %0 to i32
- %1 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @d_sh, i32 0, i32 2), align 2
+ %1 = load i16, ptr getelementptr inbounds ([16 x i16], ptr @d_sh, i32 0, i32 2), align 2
%conv2 = sext i16 %1 to i32
%cmp = icmp eq i32 %conv1, %conv2
%conv3 = zext i1 %cmp to i32
ret i32 %conv3
}
-define i1 @or_icmp_ugt(i32 %arg, i8* %ptr) {
+define i1 @or_icmp_ugt(i32 %arg, ptr %ptr) {
; CHECK-LABEL: @or_icmp_ugt(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[PTR:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[MUL:%.*]] = shl nuw nsw i32 [[TMP2]], 1
@@ -145,7 +143,7 @@ define i1 @or_icmp_ugt(i32 %arg, i8* %ptr) {
; CHECK-NEXT: ret i1 [[OR]]
;
entry:
- %0 = load i8, i8* %ptr
+ %0 = load i8, ptr %ptr
%1 = zext i8 %0 to i32
%mul = shl nuw nsw i32 %1, 1
%add0 = add nuw nsw i32 %mul, 6
@@ -158,11 +156,11 @@ entry:
; We currently only handle truncs as sinks, so a uxt will still be needed for
; the icmp ugt instruction.
-define void @urem_trunc_icmps(i16** %in, i32* %g, i32* %k) {
+define void @urem_trunc_icmps(ptr %in, ptr %g, ptr %k) {
; CHECK-LABEL: @urem_trunc_icmps(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[PTR:%.*]] = load i16*, i16** [[IN:%.*]], align 4
-; CHECK-NEXT: [[LD:%.*]] = load i16, i16* [[PTR]], align 2
+; CHECK-NEXT: [[PTR:%.*]] = load ptr, ptr [[IN:%.*]], align 4
+; CHECK-NEXT: [[LD:%.*]] = load i16, ptr [[PTR]], align 2
; CHECK-NEXT: [[CMP_I:%.*]] = icmp eq i16 [[LD]], 0
; CHECK-NEXT: br i1 [[CMP_I]], label [[EXIT:%.*]], label [[COND_FALSE_I:%.*]]
; CHECK: cond.false.i:
@@ -173,8 +171,8 @@ define void @urem_trunc_icmps(i16** %in, i32* %g, i32* %k) {
; CHECK-NEXT: [[COND_IN_I_OFF0:%.*]] = phi i8 [ [[EXTRACT_T]], [[COND_FALSE_I]] ], [ [[ADD:%.*]], [[FOR_INC:%.*]] ]
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[COND_IN_I_OFF0]], 7
; CHECK-NEXT: [[CONV5:%.*]] = zext i1 [[CMP]] to i32
-; CHECK-NEXT: store i32 [[CONV5]], i32* [[G:%.*]], align 4
-; CHECK-NEXT: [[DOTPR:%.*]] = load i32, i32* [[K:%.*]], align 4
+; CHECK-NEXT: store i32 [[CONV5]], ptr [[G:%.*]], align 4
+; CHECK-NEXT: [[DOTPR:%.*]] = load i32, ptr [[K:%.*]], align 4
; CHECK-NEXT: [[TOBOOL13150:%.*]] = icmp eq i32 [[DOTPR]], 0
; CHECK-NEXT: br i1 [[TOBOOL13150]], label [[FOR_INC]], label [[EXIT]]
; CHECK: for.inc:
@@ -184,8 +182,8 @@ define void @urem_trunc_icmps(i16** %in, i32* %g, i32* %k) {
; CHECK-NEXT: ret void
;
entry:
- %ptr = load i16*, i16** %in, align 4
- %ld = load i16, i16* %ptr, align 2
+ %ptr = load ptr, ptr %in, align 4
+ %ld = load i16, ptr %ptr, align 2
%cmp.i = icmp eq i16 %ld, 0
br i1 %cmp.i, label %exit, label %cond.false.i
@@ -198,8 +196,8 @@ body:
%cond.in.i.off0 = phi i8 [ %extract.t, %cond.false.i ], [ %add, %for.inc ]
%cmp = icmp ugt i8 %cond.in.i.off0, 7
%conv5 = zext i1 %cmp to i32
- store i32 %conv5, i32* %g, align 4
- %.pr = load i32, i32* %k, align 4
+ store i32 %conv5, ptr %g, align 4
+ %.pr = load i32, ptr %k, align 4
%tobool13150 = icmp eq i32 %.pr, 0
br i1 %tobool13150, label %for.inc, label %exit
@@ -213,10 +211,10 @@ exit:
; Check that %exp requires uxth in all cases, and will also be required to
; promote %1 for the call - unless we can generate a uadd16.
-define i32 @zext_load_sink_call(i16* %ptr, i16 %exp) {
+define i32 @zext_load_sink_call(ptr %ptr, i16 %exp) {
; CHECK-LABEL: @zext_load_sink_call(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[EXP:%.*]], 3
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP0]], [[EXP]]
; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[IF_THEN:%.*]]
@@ -230,7 +228,7 @@ define i32 @zext_load_sink_call(i16* %ptr, i16 %exp) {
; CHECK-NEXT: ret i32 [[EXITVAL]]
;
entry:
- %0 = load i16, i16* %ptr, align 4
+ %0 = load i16, ptr %ptr, align 4
%1 = add i16 %exp, 3
%cmp = icmp eq i16 %0, %exp
br i1 %cmp, label %exit, label %if.then
@@ -328,48 +326,42 @@ declare i32 @dummy(i32, i32)
@sh1 = hidden local_unnamed_addr global i16 0, align 2
@d_sh = hidden local_unnamed_addr global [16 x i16] zeroinitializer, align 2
-define i8* @two_stage_zext_trunc_mix(i32* %this, i32 %__pos1, i32 %__n1, i32** %__str, i32 %__pos2, i32 %__n2) {
+define ptr @two_stage_zext_trunc_mix(ptr %this, i32 %__pos1, i32 %__n1, ptr %__str, i32 %__pos2, i32 %__n2) {
; CHECK-LABEL: @two_stage_zext_trunc_mix(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[__SIZE__I_I_I_I:%.*]] = bitcast i32** [[__STR:%.*]] to i8*
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[__SIZE__I_I_I_I]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[__STR:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1
; CHECK-NEXT: [[TOBOOL_I_I_I_I:%.*]] = icmp eq i32 [[TMP2]], 0
-; CHECK-NEXT: [[__SIZE__I5_I_I:%.*]] = getelementptr inbounds i32*, i32** [[__STR]], i32 [[__N1:%.*]]
-; CHECK-NEXT: [[CAST:%.*]] = bitcast i32** [[__SIZE__I5_I_I]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CAST]], align 4
+; CHECK-NEXT: [[__SIZE__I5_I_I:%.*]] = getelementptr inbounds ptr, ptr [[__STR]], i32 [[__N1:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[__SIZE__I5_I_I]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 1
; CHECK-NEXT: [[COND_I_I:%.*]] = select i1 [[TOBOOL_I_I_I_I]], i32 [[TMP4]], i32 [[TMP3]]
-; CHECK-NEXT: [[__SIZE__I_I_I_I_I:%.*]] = bitcast i32* [[THIS:%.*]] to i8*
-; CHECK-NEXT: [[TMP5:%.*]] = load i8, i8* [[__SIZE__I_I_I_I_I]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[THIS:%.*]], align 4
; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 1
; CHECK-NEXT: [[TOBOOL_I_I_I_I_I:%.*]] = icmp eq i32 [[TMP7]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS1:%.*]]
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS2:%.*]]
-; CHECK-NEXT: [[RES:%.*]] = select i1 [[TOBOOL_I_I_I_I_I]], i8* [[TMP8]], i8* [[TMP9]]
-; CHECK-NEXT: ret i8* [[RES]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[__STR]], i32 [[__POS1:%.*]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[__STR]], i32 [[__POS2:%.*]]
+; CHECK-NEXT: [[RES:%.*]] = select i1 [[TOBOOL_I_I_I_I_I]], ptr [[TMP8]], ptr [[TMP9]]
+; CHECK-NEXT: ret ptr [[RES]]
;
entry:
- %__size_.i.i.i.i = bitcast i32** %__str to i8*
- %0 = load i8, i8* %__size_.i.i.i.i, align 4
+ %0 = load i8, ptr %__str, align 4
%1 = and i8 %0, 1
%tobool.i.i.i.i = icmp eq i8 %1, 0
- %__size_.i5.i.i = getelementptr inbounds i32*, i32** %__str, i32 %__n1
- %cast = bitcast i32** %__size_.i5.i.i to i32*
- %2 = load i32, i32* %cast, align 4
+ %__size_.i5.i.i = getelementptr inbounds ptr, ptr %__str, i32 %__n1
+ %2 = load i32, ptr %__size_.i5.i.i, align 4
%3 = lshr i8 %0, 1
%4 = zext i8 %3 to i32
%cond.i.i = select i1 %tobool.i.i.i.i, i32 %4, i32 %2
- %__size_.i.i.i.i.i = bitcast i32* %this to i8*
- %5 = load i8, i8* %__size_.i.i.i.i.i, align 4
+ %5 = load i8, ptr %this, align 4
%6 = and i8 %5, 1
%tobool.i.i.i.i.i = icmp eq i8 %6, 0
- %7 = getelementptr inbounds i8, i8* %__size_.i.i.i.i, i32 %__pos1
- %8 = getelementptr inbounds i8, i8* %__size_.i.i.i.i, i32 %__pos2
- %res = select i1 %tobool.i.i.i.i.i, i8* %7, i8* %8
- ret i8* %res
+ %7 = getelementptr inbounds i8, ptr %__str, i32 %__pos1
+ %8 = getelementptr inbounds i8, ptr %__str, i32 %__pos2
+ %res = select i1 %tobool.i.i.i.i.i, ptr %7, ptr %8
+ ret ptr %res
}
define i8 @search_through_zext_1(i8 zeroext %a, i8 zeroext %b, i16 zeroext %c) {
@@ -560,12 +552,12 @@ if.end:
ret i8 %retval
}
-define i8 @search_through_zext_load(i8* %a, i8 zeroext %b, i16 zeroext %c) {
+define i8 @search_through_zext_load(ptr %a, i8 zeroext %b, i16 zeroext %c) {
; CHECK-LABEL: @search_through_zext_load(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[C:%.*]] to i32
-; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8* [[A:%.*]], align 1
+; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr [[A:%.*]], align 1
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[LOAD]] to i32
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
@@ -580,7 +572,7 @@ define i8 @search_through_zext_load(i8* %a, i8 zeroext %b, i16 zeroext %c) {
; CHECK-NEXT: ret i8 [[TMP3]]
;
entry:
- %load = load i8, i8* %a
+ %load = load i8, ptr %a
%conv = zext i8 %load to i16
%cmp1 = icmp ult i16 %conv, %c
br i1 %cmp1, label %if.then, label %if.end
@@ -664,7 +656,7 @@ if.end:
ret i16 %retval
}
-define i16 @trunc_sink_less_than_store(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i8 zeroext %d, i8* %e) {
+define i16 @trunc_sink_less_than_store(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i8 zeroext %d, ptr %e) {
; CHECK-LABEL: @trunc_sink_less_than_store(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[B:%.*]] to i32
@@ -678,7 +670,7 @@ define i16 @trunc_sink_less_than_store(i16 zeroext %a, i16 zeroext %b, i16 zeroe
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[SUB]], 255
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP2]], [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[ADD]] to i8
-; CHECK-NEXT: store i8 [[TMP5]], i8* [[E:%.*]], align 1
+; CHECK-NEXT: store i8 [[TMP5]], ptr [[E:%.*]], align 1
; CHECK-NEXT: br label [[IF_END]]
; CHECK: if.end:
; CHECK-NEXT: [[RETVAL:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SUB]], [[IF_THEN]] ]
@@ -693,7 +685,7 @@ entry:
if.then:
%trunc = trunc i16 %sub to i8
%add = add nuw i8 %d, %trunc
- store i8 %add, i8* %e
+ store i8 %add, ptr %e
br label %if.end
if.end:
@@ -804,25 +796,25 @@ exit:
ret i32 %retval
}
-define void @search_back_through_trunc(i8* %a, i8* %b, i8* %c, i8* %d, i16* %e) {
+define void @search_back_through_trunc(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e) {
; CHECK-LABEL: @search_back_through_trunc(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[TMP1]], 8
-; CHECK-NEXT: [[TMP2:%.*]] = load i8, i8* [[B:%.*]], align 1
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[B:%.*]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32
; CHECK-NEXT: [[OR109:%.*]] = or i32 [[SHL]], [[TMP3]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i8, i8* [[C:%.*]], align 1
+; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[C:%.*]], align 1
; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP4]] to i32
; CHECK-NEXT: [[SHL120:%.*]] = shl nuw i32 [[TMP5]], 8
-; CHECK-NEXT: [[TMP6:%.*]] = load i8, i8* [[D:%.*]], align 1
+; CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[D:%.*]], align 1
; CHECK-NEXT: [[TMP7:%.*]] = zext i8 [[TMP6]] to i32
; CHECK-NEXT: [[OR123:%.*]] = or i32 [[SHL120]], [[TMP7]]
; CHECK-NEXT: [[CMP133:%.*]] = icmp eq i32 [[OR109]], [[OR123]]
; CHECK-NEXT: br i1 [[CMP133]], label [[IF_END183:%.*]], label [[IF_ELSE136:%.*]]
; CHECK: if.else136:
-; CHECK-NEXT: [[TMP8:%.*]] = load i16, i16* [[E:%.*]], align 2
+; CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr [[E:%.*]], align 2
; CHECK-NEXT: [[TMP9:%.*]] = zext i16 [[TMP8]] to i32
; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP9]], 255
; CHECK-NEXT: [[EXTRACT856:%.*]] = lshr i32 [[TMP9]], 8
@@ -832,29 +824,29 @@ define void @search_back_through_trunc(i8* %a, i8* %b, i8* %c, i8* %d, i16* %e)
; CHECK-NEXT: [[W_0_OFF0:%.*]] = phi i32 [ [[TMP10]], [[IF_ELSE136]] ], [ [[TMP3]], [[ENTRY:%.*]] ]
; CHECK-NEXT: [[W_0_OFF8:%.*]] = phi i32 [ [[TMP11]], [[IF_ELSE136]] ], [ [[TMP5]], [[ENTRY]] ]
; CHECK-NEXT: [[TMP12:%.*]] = trunc i32 [[W_0_OFF8]] to i8
-; CHECK-NEXT: store i8 [[TMP12]], i8* [[C]], align 1
+; CHECK-NEXT: store i8 [[TMP12]], ptr [[C]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = trunc i32 [[W_0_OFF0]] to i8
-; CHECK-NEXT: store i8 [[TMP13]], i8* [[D]], align 1
+; CHECK-NEXT: store i8 [[TMP13]], ptr [[D]], align 1
; CHECK-NEXT: ret void
;
entry:
- %0 = load i8, i8* %a, align 1
+ %0 = load i8, ptr %a, align 1
%conv106 = zext i8 %0 to i16
%shl = shl nuw i16 %conv106, 8
- %1 = load i8, i8* %b, align 1
+ %1 = load i8, ptr %b, align 1
%conv108 = zext i8 %1 to i16
%or109 = or i16 %shl, %conv108
- %2 = load i8, i8* %c, align 1
+ %2 = load i8, ptr %c, align 1
%conv119 = zext i8 %2 to i16
%shl120 = shl nuw i16 %conv119, 8
- %3 = load i8, i8* %d, align 1
+ %3 = load i8, ptr %d, align 1
%conv122 = zext i8 %3 to i16
%or123 = or i16 %shl120, %conv122
%cmp133 = icmp eq i16 %or109, %or123
br i1 %cmp133, label %if.end183, label %if.else136
if.else136:
- %4 = load i16, i16* %e, align 2
+ %4 = load i16, ptr %e, align 2
%extract.t854 = trunc i16 %4 to i8
%extract856 = lshr i16 %4, 8
%extract.t857 = trunc i16 %extract856 to i8
@@ -863,8 +855,8 @@ if.else136:
if.end183:
%w.0.off0 = phi i8 [ %extract.t854, %if.else136 ], [ %1, %entry ]
%w.0.off8 = phi i8 [ %extract.t857, %if.else136 ], [ %2, %entry ]
- store i8 %w.0.off8, i8* %c, align 1
- store i8 %w.0.off0, i8* %d, align 1
+ store i8 %w.0.off8, ptr %c, align 1
+ store i8 %w.0.off0, ptr %d, align 1
ret void
}
@@ -878,17 +870,17 @@ if.end183:
define void @and_trunc_two_zext() {
; CHECK-LABEL: @and_trunc_two_zext(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @c, align 2
-; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* @b, align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @c, align 2
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @b, align 2
; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
-; CHECK-NEXT: store i32 [[CONV]], i32* @f, align 4
+; CHECK-NEXT: store i32 [[CONV]], ptr @f, align 4
; CHECK-NEXT: [[TMP2:%.*]] = trunc i16 [[TMP1]] to i8
; CHECK-NEXT: [[CONV1:%.*]] = and i8 [[TMP2]], 1
-; CHECK-NEXT: store i8 [[CONV1]], i8* @e, align 1
-; CHECK-NEXT: [[TMP3:%.*]] = load i8, i8* @a, align 1
+; CHECK-NEXT: store i8 [[CONV1]], ptr @e, align 1
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr @a, align 1
; CHECK-NEXT: [[NARROW:%.*]] = mul nuw i8 [[TMP3]], [[CONV1]]
; CHECK-NEXT: [[MUL:%.*]] = zext i8 [[NARROW]] to i32
-; CHECK-NEXT: store i32 [[MUL]], i32* @d, align 4
+; CHECK-NEXT: store i32 [[MUL]], ptr @d, align 4
; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[NARROW]] to i16
; CHECK-NEXT: [[CONV5:%.*]] = or i16 [[TMP0]], [[TMP4]]
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[CONV5]], 0
@@ -899,17 +891,17 @@ define void @and_trunc_two_zext() {
; CHECK-NEXT: ret void
;
entry:
- %0 = load i16, i16* @c, align 2
- %1 = load i16, i16* @b, align 2
+ %0 = load i16, ptr @c, align 2
+ %1 = load i16, ptr @b, align 2
%conv = sext i16 %1 to i32
- store i32 %conv, i32* @f, align 4
+ store i32 %conv, ptr @f, align 4
%2 = trunc i16 %1 to i8
%conv1 = and i8 %2, 1
- store i8 %conv1, i8* @e, align 1
- %3 = load i8, i8* @a, align 1
+ store i8 %conv1, ptr @e, align 1
+ %3 = load i8, ptr @a, align 1
%narrow = mul nuw i8 %3, %conv1
%mul = zext i8 %narrow to i32
- store i32 %mul, i32* @d, align 4
+ store i32 %mul, ptr @d, align 4
%4 = zext i8 %narrow to i16
%conv5 = or i16 %0, %4
%tobool = icmp eq i16 %conv5, 0
@@ -925,10 +917,10 @@ if.end:
define void @zext_urem_trunc() {
; CHECK-LABEL: @zext_urem_trunc(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @c, align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @c, align 2
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[TMP0]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = load i8, i8* @e, align 1
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @e, align 1
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32
; CHECK-NEXT: br i1 [[CMP]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
; CHECK: cond.false:
@@ -938,13 +930,13 @@ define void @zext_urem_trunc() {
; CHECK: cond.end:
; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP4]], [[COND_FALSE]] ], [ [[TMP3]], [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[COND]] to i8
-; CHECK-NEXT: store i8 [[TMP5]], i8* @a, align 1
+; CHECK-NEXT: store i8 [[TMP5]], ptr @a, align 1
; CHECK-NEXT: ret void
;
entry:
- %0 = load i16, i16* @c, align 2
+ %0 = load i16, ptr @c, align 2
%cmp = icmp eq i16 %0, 0
- %1 = load i8, i8* @e, align 1
+ %1 = load i8, ptr @e, align 1
br i1 %cmp, label %cond.end, label %cond.false
cond.false:
@@ -955,78 +947,78 @@ cond.false:
cond.end:
%cond = phi i8 [ %rem.zext, %cond.false ], [ %1, %entry ]
- store i8 %cond, i8* @a, align 1
+ store i8 %cond, ptr @a, align 1
ret void
}
-define i1 @dont_replace_trunc_1(i8* %a, i16* %b, i16* %c, i32* %d, i8* %e, i32* %f) {
+define i1 @dont_replace_trunc_1(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f) {
; CHECK-LABEL: @dont_replace_trunc_1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[C:%.*]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* [[B:%.*]], align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[C:%.*]], align 2
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B:%.*]], align 2
; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
-; CHECK-NEXT: store i32 [[CONV]], i32* [[F:%.*]], align 4
+; CHECK-NEXT: store i32 [[CONV]], ptr [[F:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = trunc i16 [[TMP1]] to i8
; CHECK-NEXT: [[CONV1:%.*]] = and i8 [[TMP2]], 1
-; CHECK-NEXT: store i8 [[CONV1]], i8* [[E:%.*]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = load i8, i8* [[A:%.*]], align 1
+; CHECK-NEXT: store i8 [[CONV1]], ptr [[E:%.*]], align 1
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[A:%.*]], align 1
; CHECK-NEXT: [[NARROW:%.*]] = mul nuw i8 [[TMP3]], [[CONV1]]
; CHECK-NEXT: [[MUL:%.*]] = zext i8 [[NARROW]] to i32
-; CHECK-NEXT: store i32 [[MUL]], i32* [[D:%.*]], align 4
+; CHECK-NEXT: store i32 [[MUL]], ptr [[D:%.*]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[NARROW]] to i16
; CHECK-NEXT: [[CONV5:%.*]] = or i16 [[TMP0]], [[TMP4]]
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[CONV5]], 0
; CHECK-NEXT: ret i1 [[TOBOOL]]
;
entry:
- %0 = load i16, i16* %c, align 2
- %1 = load i16, i16* %b, align 2
+ %0 = load i16, ptr %c, align 2
+ %1 = load i16, ptr %b, align 2
%conv = sext i16 %1 to i32
- store i32 %conv, i32* %f, align 4
+ store i32 %conv, ptr %f, align 4
%2 = trunc i16 %1 to i8
%conv1 = and i8 %2, 1
- store i8 %conv1, i8* %e, align 1
- %3 = load i8, i8* %a, align 1
+ store i8 %conv1, ptr %e, align 1
+ %3 = load i8, ptr %a, align 1
%narrow = mul nuw i8 %3, %conv1
%mul = zext i8 %narrow to i32
- store i32 %mul, i32* %d, align 4
+ store i32 %mul, ptr %d, align 4
%4 = zext i8 %narrow to i16
%conv5 = or i16 %0, %4
%tobool = icmp eq i16 %conv5, 0
ret i1 %tobool
}
-define i32 @dont_return_inserted_trunc(i16* %a, i8* %b) {
+define i32 @dont_return_inserted_trunc(ptr %a, ptr %b) {
; CHECK-LABEL: @dont_return_inserted_trunc(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[TMP0]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP1]], 8
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[CMP]], i32 [[TMP1]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[NARROW]], 255
-; CHECK-NEXT: [[TMP3:%.*]] = load i8, i8* [[B:%.*]], align 1
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[B:%.*]], align 1
; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP4]], [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[OR]] to i8
-; CHECK-NEXT: store i8 [[TMP5]], i8* [[B]], align 1
+; CHECK-NEXT: store i8 [[TMP5]], ptr [[B]], align 1
; CHECK-NEXT: ret i32 [[OR]]
;
entry:
- %0 = load i16, i16* %a, align 2
+ %0 = load i16, ptr %a, align 2
%cmp = icmp ugt i16 %0, 8
%narrow = select i1 %cmp, i16 %0, i16 0
%cond = trunc i16 %narrow to i8
- %1 = load i8, i8* %b, align 1
+ %1 = load i8, ptr %b, align 1
%or = or i8 %1, %cond
- store i8 %or, i8* %b, align 1
+ store i8 %or, ptr %b, align 1
%conv5 = zext i8 %or to i32
ret i32 %conv5
}
-define i32 @replace_trunk_with_mask(i16* %a) {
+define i32 @replace_trunk_with_mask(ptr %a) {
; CHECK-LABEL: @replace_trunk_with_mask(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[TMP0]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
@@ -1040,7 +1032,7 @@ define i32 @replace_trunk_with_mask(i16* %a) {
; CHECK-NEXT: ret i32 [[COND]]
;
entry:
- %0 = load i16, i16* %a
+ %0 = load i16, ptr %a
%cmp = icmp eq i16 %0, 0
br i1 %cmp, label %cond.end, label %cond.false
@@ -1056,10 +1048,10 @@ cond.end:
ret i32 %cond
}
-define float @test_i8_sitofp(i8* %ptr, i8 %arg) {
+define float @test_i8_sitofp(ptr %ptr, i8 %arg) {
; CHECK-LABEL: @test_i8_sitofp(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[PTR:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], [[ARG:%.*]]
; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[IF_END:%.*]]
; CHECK: if.end:
@@ -1071,7 +1063,7 @@ define float @test_i8_sitofp(i8* %ptr, i8 %arg) {
; CHECK-NEXT: ret float [[RES]]
;
entry:
- %0 = load i8, i8* %ptr, align 1
+ %0 = load i8, ptr %ptr, align 1
%cmp = icmp eq i8 %0, %arg
br i1 %cmp, label %exit, label %if.end
@@ -1085,10 +1077,10 @@ exit:
ret float %res
}
-define float @test_i16_sitofp(i16* %ptr, i16 %arg) {
+define float @test_i16_sitofp(ptr %ptr, i16 %arg) {
; CHECK-LABEL: @test_i16_sitofp(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[PTR:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[TMP0]], [[ARG:%.*]]
; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[IF_END:%.*]]
; CHECK: if.end:
@@ -1100,7 +1092,7 @@ define float @test_i16_sitofp(i16* %ptr, i16 %arg) {
; CHECK-NEXT: ret float [[RES]]
;
entry:
- %0 = load i16, i16* %ptr, align 1
+ %0 = load i16, ptr %ptr, align 1
%cmp = icmp eq i16 %0, %arg
br i1 %cmp, label %exit, label %if.end
diff --git a/llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll b/llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll
index a8b8c411cb785..df2544bf81d3e 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
-define i32 @clear_structures(i8* nocapture readonly %fmt, [1 x i32] %ap.coerce, i8* %out, void (i32, i8*)* nocapture %write) {
+define i32 @clear_structures(ptr nocapture readonly %fmt, [1 x i32] %ap.coerce, ptr %out, ptr nocapture %write) {
; CHECK-LABEL: @clear_structures(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[WHILE_COND_OUTER:%.*]]
; CHECK: while.cond.outer:
-; CHECK-NEXT: [[FMT_ADDR_0_PH:%.*]] = phi i8* [ [[FMT:%.*]], [[ENTRY:%.*]] ], [ [[FMT_ADDR_3:%.*]], [[WHILE_COND_OUTER_BACKEDGE:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[FMT_ADDR_0_PH]], align 1
+; CHECK-NEXT: [[FMT_ADDR_0_PH:%.*]] = phi ptr [ [[FMT:%.*]], [[ENTRY:%.*]] ], [ [[FMT_ADDR_3:%.*]], [[WHILE_COND_OUTER_BACKEDGE:%.*]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[FMT_ADDR_0_PH]], align 1
; CHECK-NEXT: br label [[WHILE_COND:%.*]]
; CHECK: while.cond:
; CHECK-NEXT: switch i8 [[TMP0]], label [[WHILE_COND]] [
@@ -16,9 +16,9 @@ define i32 @clear_structures(i8* nocapture readonly %fmt, [1 x i32] %ap.coerce,
; CHECK-NEXT: ]
; CHECK: while.cond2:
; CHECK-NEXT: [[FLAGS_0:%.*]] = phi i32 [ [[OR:%.*]], [[WHILE_COND2]] ], [ 0, [[WHILE_COND]] ]
-; CHECK-NEXT: [[FMT_ADDR_0_PN:%.*]] = phi i8* [ [[FMT_ADDR_1:%.*]], [[WHILE_COND2]] ], [ [[FMT_ADDR_0_PH]], [[WHILE_COND]] ]
-; CHECK-NEXT: [[FMT_ADDR_1]] = getelementptr inbounds i8, i8* [[FMT_ADDR_0_PN]], i32 1
-; CHECK-NEXT: [[TMP1:%.*]] = load i8, i8* [[FMT_ADDR_1]], align 1
+; CHECK-NEXT: [[FMT_ADDR_0_PN:%.*]] = phi ptr [ [[FMT_ADDR_1:%.*]], [[WHILE_COND2]] ], [ [[FMT_ADDR_0_PH]], [[WHILE_COND]] ]
+; CHECK-NEXT: [[FMT_ADDR_1]] = getelementptr inbounds i8, ptr [[FMT_ADDR_0_PN]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[FMT_ADDR_1]], align 1
; CHECK-NEXT: [[SUB:%.*]] = add i8 [[TMP1]], -32
; CHECK-NEXT: [[CONV6:%.*]] = zext i8 [[SUB]] to i32
; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[CONV6]]
@@ -36,8 +36,8 @@ define i32 @clear_structures(i8* nocapture readonly %fmt, [1 x i32] %ap.coerce,
; CHECK-NEXT: [[CMP20:%.*]] = icmp eq i8 [[TMP1]], 46
; CHECK-NEXT: br i1 [[CMP20]], label [[IF_THEN22:%.*]], label [[COND_END:%.*]]
; CHECK: if.then22:
-; CHECK-NEXT: [[INCDEC_PTR23:%.*]] = getelementptr inbounds i8, i8* [[FMT_ADDR_0_PN]], i32 2
-; CHECK-NEXT: [[DOTPR74:%.*]] = load i8, i8* [[INCDEC_PTR23]], align 1
+; CHECK-NEXT: [[INCDEC_PTR23:%.*]] = getelementptr inbounds i8, ptr [[FMT_ADDR_0_PN]], i32 2
+; CHECK-NEXT: [[DOTPR74:%.*]] = load i8, ptr [[INCDEC_PTR23]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[DOTPR74]] to i32
; CHECK-NEXT: [[DOTPR74_OFF:%.*]] = add i32 [[TMP3]], -48
; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[DOTPR74_OFF]], 10
@@ -45,14 +45,14 @@ define i32 @clear_structures(i8* nocapture readonly %fmt, [1 x i32] %ap.coerce,
; CHECK: while.cond24:
; CHECK-NEXT: br label [[WHILE_COND24]]
; CHECK: cond.end:
-; CHECK-NEXT: [[FMT_ADDR_3]] = phi i8* [ [[FMT_ADDR_1]], [[WHILE_END18_SPLIT]] ], [ [[INCDEC_PTR23]], [[IF_THEN22]] ]
+; CHECK-NEXT: [[FMT_ADDR_3]] = phi ptr [ [[FMT_ADDR_1]], [[WHILE_END18_SPLIT]] ], [ [[INCDEC_PTR23]], [[IF_THEN22]] ]
; CHECK-NEXT: [[AND39:%.*]] = and i32 [[FLAGS_0]], 2048
; CHECK-NEXT: [[TOBOOL40:%.*]] = icmp eq i32 [[AND39]], 0
; CHECK-NEXT: br i1 [[TOBOOL40]], label [[WHILE_COND_OUTER_BACKEDGE]], label [[IF_THEN43:%.*]]
; CHECK: while.cond.outer.backedge:
; CHECK-NEXT: br label [[WHILE_COND_OUTER]]
; CHECK: if.then43:
-; CHECK-NEXT: tail call void [[WRITE:%.*]](i32 43, i8* [[OUT:%.*]])
+; CHECK-NEXT: tail call void [[WRITE:%.*]](i32 43, ptr [[OUT:%.*]])
; CHECK-NEXT: br label [[WHILE_COND_OUTER_BACKEDGE]]
; CHECK: while.end48:
; CHECK-NEXT: ret i32 undef
@@ -61,8 +61,8 @@ entry:
br label %while.cond.outer
while.cond.outer:
- %fmt.addr.0.ph = phi i8* [ %fmt, %entry ], [ %fmt.addr.3, %while.cond.outer.backedge ]
- %0 = load i8, i8* %fmt.addr.0.ph, align 1
+ %fmt.addr.0.ph = phi ptr [ %fmt, %entry ], [ %fmt.addr.3, %while.cond.outer.backedge ]
+ %0 = load i8, ptr %fmt.addr.0.ph, align 1
br label %while.cond
while.cond:
@@ -73,9 +73,9 @@ while.cond:
while.cond2:
%flags.0 = phi i32 [ %or, %while.cond2 ], [ 0, %while.cond ]
- %fmt.addr.0.pn = phi i8* [ %fmt.addr.1, %while.cond2 ], [ %fmt.addr.0.ph, %while.cond ]
- %fmt.addr.1 = getelementptr inbounds i8, i8* %fmt.addr.0.pn, i32 1
- %1 = load i8, i8* %fmt.addr.1, align 1
+ %fmt.addr.0.pn = phi ptr [ %fmt.addr.1, %while.cond2 ], [ %fmt.addr.0.ph, %while.cond ]
+ %fmt.addr.1 = getelementptr inbounds i8, ptr %fmt.addr.0.pn, i32 1
+ %1 = load i8, ptr %fmt.addr.1, align 1
%sub = add i8 %1, -32
%conv6 = zext i8 %sub to i32
%shl = shl i32 1, %conv6
@@ -97,8 +97,8 @@ while.end18.split:
br i1 %cmp20, label %if.then22, label %cond.end
if.then22:
- %incdec.ptr23 = getelementptr inbounds i8, i8* %fmt.addr.0.pn, i32 2
- %.pr74 = load i8, i8* %incdec.ptr23, align 1
+ %incdec.ptr23 = getelementptr inbounds i8, ptr %fmt.addr.0.pn, i32 2
+ %.pr74 = load i8, ptr %incdec.ptr23, align 1
%.pr74.off = add i8 %.pr74, -48
%3 = icmp ult i8 %.pr74.off, 10
br i1 %3, label %while.cond24, label %cond.end
@@ -107,7 +107,7 @@ while.cond24:
br label %while.cond24
cond.end:
- %fmt.addr.3 = phi i8* [ %fmt.addr.1, %while.end18.split ], [ %incdec.ptr23, %if.then22 ]
+ %fmt.addr.3 = phi ptr [ %fmt.addr.1, %while.end18.split ], [ %incdec.ptr23, %if.then22 ]
%and39 = and i32 %flags.0, 2048
%tobool40 = icmp eq i32 %and39, 0
br i1 %tobool40, label %while.cond.outer.backedge, label %if.then43
@@ -116,7 +116,7 @@ while.cond.outer.backedge:
br label %while.cond.outer
if.then43:
- tail call void %write(i32 43, i8* %out) #1
+ tail call void %write(i32 43, ptr %out) #1
br label %while.cond.outer.backedge
while.end48:
diff --git a/llvm/test/Transforms/TypePromotion/ARM/icmps.ll b/llvm/test/Transforms/TypePromotion/ARM/icmps.ll
index ed179a033368e..842aab121b96f 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/icmps.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/icmps.ll
@@ -164,28 +164,26 @@ define i32 @dsp_var(i8 zeroext %x, i8 zeroext %y) {
ret i32 %res
}
-define void @store_dsp_res(i8* %in, i8* %out, i8 %compare) {
+define void @store_dsp_res(ptr %in, ptr %out, i8 %compare) {
; CHECK-LABEL: @store_dsp_res(
-; CHECK-NEXT: [[FIRST:%.*]] = getelementptr inbounds i8, i8* [[IN:%.*]], i32 0
-; CHECK-NEXT: [[SECOND:%.*]] = getelementptr inbounds i8, i8* [[IN]], i32 1
-; CHECK-NEXT: [[LD0:%.*]] = load i8, i8* [[FIRST]], align 1
-; CHECK-NEXT: [[LD1:%.*]] = load i8, i8* [[SECOND]], align 1
+; CHECK-NEXT: [[SECOND:%.*]] = getelementptr inbounds i8, ptr [[IN:%.*]], i32 1
+; CHECK-NEXT: [[LD0:%.*]] = load i8, ptr [[IN]], align 1
+; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[SECOND]], align 1
; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[LD0]], -1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[COMPARE:%.*]], [[LD1]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[COMPARE]], i8 [[XOR]]
; CHECK-NEXT: [[SUB:%.*]] = sub i8 [[LD0]], [[SELECT]]
-; CHECK-NEXT: store i8 [[SUB]], i8* [[OUT:%.*]], align 1
+; CHECK-NEXT: store i8 [[SUB]], ptr [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
- %first = getelementptr inbounds i8, i8* %in, i32 0
- %second = getelementptr inbounds i8, i8* %in, i32 1
- %ld0 = load i8, i8* %first
- %ld1 = load i8, i8* %second
+ %second = getelementptr inbounds i8, ptr %in, i32 1
+ %ld0 = load i8, ptr %in
+ %ld1 = load i8, ptr %second
%xor = xor i8 %ld0, -1
%cmp = icmp ult i8 %compare, %ld1
%select = select i1 %cmp, i8 %compare, i8 %xor
%sub = sub i8 %ld0, %select
- store i8 %sub, i8* %out, align 1
+ store i8 %sub, ptr %out, align 1
ret void
}
@@ -220,15 +218,15 @@ entry:
ret i32 %res
}
-define i32 @icmp_eq_minus_one(i8* %ptr) {
+define i32 @icmp_eq_minus_one(ptr %ptr) {
; CHECK-LABEL: @icmp_eq_minus_one(
-; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8* [[PTR:%.*]], align 1
+; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[LOAD]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[LOAD]], -1
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[CONV]], i32 -1
; CHECK-NEXT: ret i32 [[RET]]
;
- %load = load i8, i8* %ptr, align 1
+ %load = load i8, ptr %ptr, align 1
%conv = zext i8 %load to i32
%cmp = icmp eq i8 %load, -1
%ret = select i1 %cmp, i32 %conv, i32 -1
@@ -250,28 +248,28 @@ define i32 @icmp_not(i16 zeroext %arg0, i16 zeroext %arg1) {
ret i32 %res
}
-define i32 @icmp_i1(i1* %arg0, i1 zeroext %arg1, i32 %a, i32 %b) {
+define i32 @icmp_i1(ptr %arg0, i1 zeroext %arg1, i32 %a, i32 %b) {
; CHECK-LABEL: @icmp_i1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[LOAD:%.*]] = load i1, i1* [[ARG0:%.*]], align 1
+; CHECK-NEXT: [[LOAD:%.*]] = load i1, ptr [[ARG0:%.*]], align 1
; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[LOAD]], true
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i1 [[ARG1:%.*]], [[NOT]]
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 [[A:%.*]], i32 [[B:%.*]]
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
- %load = load i1, i1* %arg0
+ %load = load i1, ptr %arg0
%not = xor i1 %load, 1
%cmp = icmp eq i1 %arg1, %not
%res = select i1 %cmp, i32 %a, i32 %b
ret i32 %res
}
-define i32 @icmp_i7(i7* %arg0, i7 zeroext %arg1, i32 %a, i32 %b) {
+define i32 @icmp_i7(ptr %arg0, i7 zeroext %arg1, i32 %a, i32 %b) {
; CHECK-LABEL: @icmp_i7(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i7 [[ARG1:%.*]] to i32
-; CHECK-NEXT: [[LOAD:%.*]] = load i7, i7* [[ARG0:%.*]], align 1
+; CHECK-NEXT: [[LOAD:%.*]] = load i7, ptr [[ARG0:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i7 [[LOAD]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP1]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], [[ADD]]
@@ -279,7 +277,7 @@ define i32 @icmp_i7(i7* %arg0, i7 zeroext %arg1, i32 %a, i32 %b) {
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
- %load = load i7, i7* %arg0
+ %load = load i7, ptr %arg0
%add = add nuw i7 %load, 1
%cmp = icmp ult i7 %arg1, %add
%res = select i1 %cmp, i32 %a, i32 %b
@@ -301,10 +299,10 @@ define i32 @icmp_i15(i15 zeroext %arg0, i15 zeroext %arg1) {
ret i32 %res
}
-define i32 @icmp_minus_imm(i8* %a) {
+define i32 @icmp_minus_imm(ptr %a) {
; CHECK-LABEL: @icmp_minus_imm(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[ADD_I:%.*]] = add i32 [[TMP1]], -7
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[ADD_I]], -5
@@ -312,17 +310,17 @@ define i32 @icmp_minus_imm(i8* %a) {
; CHECK-NEXT: ret i32 [[CONV1]]
;
entry:
- %0 = load i8, i8* %a, align 1
+ %0 = load i8, ptr %a, align 1
%add.i = add i8 %0, -7
%cmp = icmp ugt i8 %add.i, -5
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
-define i32 @icmp_minus_imm_noncanonicalcmp(i8* %a) {
+define i32 @icmp_minus_imm_noncanonicalcmp(ptr %a) {
; CHECK-LABEL: @icmp_minus_imm_noncanonicalcmp(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[ADD_I:%.*]] = add i32 [[TMP1]], -7
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 -5, [[ADD_I]]
@@ -330,14 +328,14 @@ define i32 @icmp_minus_imm_noncanonicalcmp(i8* %a) {
; CHECK-NEXT: ret i32 [[CONV1]]
;
entry:
- %0 = load i8, i8* %a, align 1
+ %0 = load i8, ptr %a, align 1
%add.i = add i8 %0, -7
%cmp = icmp ult i8 -5, %add.i
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
-define void @mul_with_neg_imm(i32, i32* %b) {
+define void @mul_with_neg_imm(i32, ptr %b) {
; CHECK-LABEL: @mul_with_neg_imm(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0:%.*]] to i8
@@ -347,7 +345,7 @@ define void @mul_with_neg_imm(i32, i32* %b) {
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[CONV_I]], 0
; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: store i32 0, i32* [[B:%.*]], align 4
+; CHECK-NEXT: store i32 0, ptr [[B:%.*]], align 4
; CHECK-NEXT: br label [[IF_END]]
; CHECK: if.end:
; CHECK-NEXT: ret void
@@ -360,7 +358,7 @@ entry:
br i1 %tobool, label %if.end, label %if.then
if.then:
- store i32 0, i32* %b, align 4
+ store i32 0, ptr %b, align 4
br label %if.end
if.end:
diff --git a/llvm/test/Transforms/TypePromotion/ARM/large-int.ll b/llvm/test/Transforms/TypePromotion/ARM/large-int.ll
index b4ad05877b643..f13c05e261fb7 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/large-int.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/large-int.ll
@@ -1,11 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=thumbv7 -passes=typepromotion -S %s -o - | FileCheck %s
-define hidden void @dont_promote_large_int(i8* %in, i64* %out) {
+define hidden void @dont_promote_large_int(ptr %in, ptr %out) {
; CHECK-LABEL: @dont_promote_large_int(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CAST:%.*]] = bitcast i8* [[IN:%.*]] to i144*
-; CHECK-NEXT: [[LOAD:%.*]] = load i144, i144* [[CAST]], align 4
+; CHECK-NEXT: [[LOAD:%.*]] = load i144, ptr [[IN:%.*]], align 4
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i144 [[LOAD]] to i98
; CHECK-NEXT: [[AND:%.*]] = and i98 [[TRUNC]], -79228162514264337593543950336
; CHECK-NEXT: [[TRUNC_1:%.*]] = trunc i98 [[TRUNC]] to i32
@@ -17,24 +16,23 @@ define hidden void @dont_promote_large_int(i8* %in, i64* %out) {
; CHECK-NEXT: [[AND_1:%.*]] = and i144 [[LOAD]], 237684487542793012780631851008
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i144 [[AND_1]], 0
; CHECK-NEXT: [[INDEX:%.*]] = select i1 [[CMP]], i32 0, i32 4
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, i64* [[OUT:%.*]], i32 [[INDEX]]
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[OUT:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[TRUNC_1]], 27
; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 0, [[MUL]]
; CHECK-NEXT: [[CAST_1:%.*]] = zext i32 [[SUB]] to i64
-; CHECK-NEXT: store i64 [[CAST_1]], i64* [[OUT]], align 4
+; CHECK-NEXT: store i64 [[CAST_1]], ptr [[OUT]], align 4
; CHECK-NEXT: br label [[BB_3]]
; CHECK: bb.2:
; CHECK-NEXT: [[CAST_2:%.*]] = zext i32 [[TRUNC_1]] to i64
; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[CAST_2]], 32
; CHECK-NEXT: [[OR:%.*]] = or i64 [[CAST_2]], [[SHL]]
-; CHECK-NEXT: store i64 [[OR]], i64* [[OUT]], align 4
+; CHECK-NEXT: store i64 [[OR]], ptr [[OUT]], align 4
; CHECK-NEXT: br label [[BB_3]]
; CHECK: bb.3:
; CHECK-NEXT: ret void
;
entry:
- %cast = bitcast i8* %in to i144*
- %load = load i144, i144* %cast, align 4
+ %load = load i144, ptr %in, align 4
%trunc = trunc i144 %load to i98
%and = and i98 %trunc, -79228162514264337593543950336
%trunc.1 = trunc i98 %trunc to i32
@@ -47,18 +45,18 @@ bb.1:
%and.1 = and i144 %load, 237684487542793012780631851008
%cmp = icmp eq i144 %and.1, 0
%index = select i1 %cmp, i32 0, i32 4
- %gep = getelementptr i64, i64* %out, i32 %index
+ %gep = getelementptr i64, ptr %out, i32 %index
%mul = mul nuw i32 %trunc.1, 27
%sub = sub nuw i32 0, %mul
%cast.1 = zext i32 %sub to i64
- store i64 %cast.1, i64* %out, align 4
+ store i64 %cast.1, ptr %out, align 4
br label %bb.3
bb.2:
%cast.2 = zext i32 %trunc.1 to i64
%shl = shl nuw i64 %cast.2, 32
%or = or i64 %cast.2, %shl
- store i64 %or, i64* %out, align 4
+ store i64 %or, ptr %out, align 4
br label %bb.3
bb.3:
diff --git a/llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll b/llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
index 004dc286628b0..6f41742e66e53 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
@@ -270,7 +270,7 @@ exit:
ret i16 %unrelated
}
-define i16 @promote_arg_return(i16 zeroext %arg1, i16 zeroext %arg2, i8* %res) {
+define i16 @promote_arg_return(i16 zeroext %arg1, i16 zeroext %arg2, ptr %res) {
; CHECK-LABEL: @promote_arg_return(
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[ARG1:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[ARG2:%.*]] to i32
@@ -278,7 +278,7 @@ define i16 @promote_arg_return(i16 zeroext %arg1, i16 zeroext %arg2, i8* %res) {
; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[ADD]], 3
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[MUL]], [[TMP2]]
; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i8
-; CHECK-NEXT: store i8 [[CONV]], i8* [[RES:%.*]], align 1
+; CHECK-NEXT: store i8 [[CONV]], ptr [[RES:%.*]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: ret i16 [[TMP3]]
;
@@ -286,11 +286,11 @@ define i16 @promote_arg_return(i16 zeroext %arg1, i16 zeroext %arg2, i8* %res) {
%mul = mul nuw nsw i16 %add, 3
%cmp = icmp ult i16 %mul, %arg2
%conv = zext i1 %cmp to i8
- store i8 %conv, i8* %res
+ store i8 %conv, ptr %res
ret i16 %arg1
}
-define i16 @signext_bitcast_phi_select(i16 signext %start, i16* %in) {
+define i16 @signext_bitcast_phi_select(i16 signext %start, ptr %in) {
; CHECK-LABEL: @signext_bitcast_phi_select(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[START:%.*]] to i32
@@ -302,8 +302,8 @@ define i16 @signext_bitcast_phi_select(i16 signext %start, i16* %in) {
; CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt i16 [[TMP1]], [[CONST]]
; CHECK-NEXT: br i1 [[CMP_I]], label [[EXIT:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: [[IDX_NEXT:%.*]] = getelementptr i16, i16* [[IN:%.*]], i32 [[IDX]]
-; CHECK-NEXT: [[LD:%.*]] = load i16, i16* [[IDX_NEXT]], align 2
+; CHECK-NEXT: [[IDX_NEXT:%.*]] = getelementptr i16, ptr [[IN:%.*]], i32 [[IDX]]
+; CHECK-NEXT: [[LD:%.*]] = load i16, ptr [[IDX_NEXT]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[LD]] to i32
; CHECK-NEXT: [[CMP1_I:%.*]] = icmp eq i32 [[TMP2]], [[IDX]]
; CHECK-NEXT: br i1 [[CMP1_I]], label [[EXIT]], label [[IF_ELSE]]
@@ -327,8 +327,8 @@ for.body:
br i1 %cmp.i, label %exit, label %if.then
if.then:
- %idx.next = getelementptr i16, i16* %in, i16 %idx
- %ld = load i16, i16* %idx.next, align 2
+ %idx.next = getelementptr i16, ptr %in, i16 %idx
+ %ld = load i16, ptr %idx.next, align 2
%cmp1.i = icmp eq i16 %ld, %idx
br i1 %cmp1.i, label %exit, label %if.else
diff --git a/llvm/test/Transforms/TypePromotion/ARM/pointers.ll b/llvm/test/Transforms/TypePromotion/ARM/pointers.ll
index 4e81310505dd3..5781dc262ffd1 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/pointers.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/pointers.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
-define void @phi_pointers(i16* %a, i16* %b, i8 zeroext %M, i8 zeroext %N) {
+define void @phi_pointers(ptr %a, ptr %b, i8 zeroext %M, i8 zeroext %N) {
; CHECK-LABEL: @phi_pointers(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[M:%.*]] to i32
@@ -9,16 +9,16 @@ define void @phi_pointers(i16* %a, i16* %b, i8 zeroext %M, i8 zeroext %N) {
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP0]], 1
; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[ADD]], [[TMP1]]
-; CHECK-NEXT: [[BASE:%.*]] = select i1 [[CMP]], i16* [[A:%.*]], i16* [[B:%.*]]
-; CHECK-NEXT: [[OTHER:%.*]] = select i1 [[CMP]], i16* [[B]], i16* [[B]]
+; CHECK-NEXT: [[BASE:%.*]] = select i1 [[CMP]], ptr [[A:%.*]], ptr [[B:%.*]]
+; CHECK-NEXT: [[OTHER:%.*]] = select i1 [[CMP]], ptr [[B]], ptr [[B]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[PTR:%.*]] = phi i16* [ [[BASE]], [[ENTRY:%.*]] ], [ [[GEP:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[PTR:%.*]] = phi ptr [ [[BASE]], [[ENTRY:%.*]] ], [ [[GEP:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[IDX:%.*]] = phi i32 [ [[AND]], [[ENTRY]] ], [ [[INC:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[LOAD:%.*]] = load i16, i16* [[PTR]], align 2
+; CHECK-NEXT: [[LOAD:%.*]] = load i16, ptr [[PTR]], align 2
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[IDX]], 1
-; CHECK-NEXT: [[GEP]] = getelementptr inbounds i16, i16* [[PTR]], i32 [[INC]]
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i16* [[GEP]], [[OTHER]]
+; CHECK-NEXT: [[GEP]] = getelementptr inbounds i16, ptr [[PTR]], i32 [[INC]]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq ptr [[GEP]], [[OTHER]]
; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -27,24 +27,24 @@ entry:
%add = add nuw i8 %M, 1
%and = and i8 %add, 1
%cmp = icmp ugt i8 %add, %N
- %base = select i1 %cmp, i16* %a, i16* %b
- %other = select i1 %cmp, i16* %b, i16* %b
+ %base = select i1 %cmp, ptr %a, ptr %b
+ %other = select i1 %cmp, ptr %b, ptr %b
br label %loop
loop:
- %ptr = phi i16* [ %base, %entry ], [ %gep, %loop ]
+ %ptr = phi ptr [ %base, %entry ], [ %gep, %loop ]
%idx = phi i8 [ %and, %entry ], [ %inc, %loop ]
- %load = load i16, i16* %ptr, align 2
+ %load = load i16, ptr %ptr, align 2
%inc = add nuw nsw i8 %idx, 1
- %gep = getelementptr inbounds i16, i16* %ptr, i8 %inc
- %cond = icmp eq i16* %gep, %other
+ %gep = getelementptr inbounds i16, ptr %ptr, i8 %inc
+ %cond = icmp eq ptr %gep, %other
br i1 %cond, label %exit, label %loop
exit:
ret void
}
-define void @phi_pointers_null(i16* %a, i16* %b, i8 zeroext %M, i8 zeroext %N) {
+define void @phi_pointers_null(ptr %a, ptr %b, i8 zeroext %M, i8 zeroext %N) {
; CHECK-LABEL: @phi_pointers_null(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[M:%.*]] to i32
@@ -52,22 +52,22 @@ define void @phi_pointers_null(i16* %a, i16* %b, i8 zeroext %M, i8 zeroext %N) {
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP0]], 1
; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[ADD]], [[TMP1]]
-; CHECK-NEXT: [[BASE:%.*]] = select i1 [[CMP]], i16* [[A:%.*]], i16* [[B:%.*]]
-; CHECK-NEXT: [[OTHER:%.*]] = select i1 [[CMP]], i16* [[B]], i16* [[B]]
-; CHECK-NEXT: [[CMP_1:%.*]] = icmp eq i16* [[BASE]], [[OTHER]]
+; CHECK-NEXT: [[BASE:%.*]] = select i1 [[CMP]], ptr [[A:%.*]], ptr [[B:%.*]]
+; CHECK-NEXT: [[OTHER:%.*]] = select i1 [[CMP]], ptr [[B]], ptr [[B]]
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp eq ptr [[BASE]], [[OTHER]]
; CHECK-NEXT: br i1 [[CMP_1]], label [[FAIL:%.*]], label [[LOOP:%.*]]
; CHECK: fail:
; CHECK-NEXT: br label [[LOOP]]
; CHECK: loop:
-; CHECK-NEXT: [[PTR:%.*]] = phi i16* [ [[BASE]], [[ENTRY:%.*]] ], [ null, [[FAIL]] ], [ [[GEP:%.*]], [[IF_THEN:%.*]] ]
+; CHECK-NEXT: [[PTR:%.*]] = phi ptr [ [[BASE]], [[ENTRY:%.*]] ], [ null, [[FAIL]] ], [ [[GEP:%.*]], [[IF_THEN:%.*]] ]
; CHECK-NEXT: [[IDX:%.*]] = phi i32 [ [[AND]], [[ENTRY]] ], [ 0, [[FAIL]] ], [ [[INC:%.*]], [[IF_THEN]] ]
-; CHECK-NEXT: [[UNDEF:%.*]] = icmp eq i16* [[PTR]], undef
+; CHECK-NEXT: [[UNDEF:%.*]] = icmp eq ptr [[PTR]], undef
; CHECK-NEXT: br i1 [[UNDEF]], label [[EXIT:%.*]], label [[IF_THEN]]
; CHECK: if.then:
-; CHECK-NEXT: [[LOAD:%.*]] = load i16, i16* [[PTR]], align 2
+; CHECK-NEXT: [[LOAD:%.*]] = load i16, ptr [[PTR]], align 2
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[IDX]], 1
-; CHECK-NEXT: [[GEP]] = getelementptr inbounds i16, i16* [[PTR]], i32 [[INC]]
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i16* [[GEP]], [[OTHER]]
+; CHECK-NEXT: [[GEP]] = getelementptr inbounds i16, ptr [[PTR]], i32 [[INC]]
+; CHECK-NEXT: [[COND:%.*]] = icmp eq ptr [[GEP]], [[OTHER]]
; CHECK-NEXT: br i1 [[COND]], label [[EXIT]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -76,34 +76,34 @@ entry:
%add = add nuw i8 %M, 1
%and = and i8 %add, 1
%cmp = icmp ugt i8 %add, %N
- %base = select i1 %cmp, i16* %a, i16* %b
- %other = select i1 %cmp, i16* %b, i16* %b
- %cmp.1 = icmp eq i16* %base, %other
+ %base = select i1 %cmp, ptr %a, ptr %b
+ %other = select i1 %cmp, ptr %b, ptr %b
+ %cmp.1 = icmp eq ptr %base, %other
br i1 %cmp.1, label %fail, label %loop
fail:
br label %loop
loop:
- %ptr = phi i16* [ %base, %entry ], [ null, %fail ], [ %gep, %if.then ]
+ %ptr = phi ptr [ %base, %entry ], [ null, %fail ], [ %gep, %if.then ]
%idx = phi i8 [ %and, %entry ], [ 0, %fail ], [ %inc, %if.then ]
- %undef = icmp eq i16* %ptr, undef
+ %undef = icmp eq ptr %ptr, undef
br i1 %undef, label %exit, label %if.then
if.then:
- %load = load i16, i16* %ptr, align 2
+ %load = load i16, ptr %ptr, align 2
%inc = add nuw nsw i8 %idx, 1
- %gep = getelementptr inbounds i16, i16* %ptr, i8 %inc
- %cond = icmp eq i16* %gep, %other
+ %gep = getelementptr inbounds i16, ptr %ptr, i8 %inc
+ %cond = icmp eq ptr %gep, %other
br i1 %cond, label %exit, label %loop
exit:
ret void
}
-declare i8 @do_something_with_ptr(i8, i16*)
+declare i8 @do_something_with_ptr(i8, ptr)
-define i8 @call_pointer(i8 zeroext %x, i8 zeroext %y, i16* %a, i16* %b) {
+define i8 @call_pointer(i8 zeroext %x, i8 zeroext %y, ptr %a, ptr %b) {
; CHECK-LABEL: @call_pointer(
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32
@@ -111,9 +111,9 @@ define i8 @call_pointer(i8 zeroext %x, i8 zeroext %y, i16* %a, i16* %b) {
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[OR]], 1
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[SHR]], 2
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[ADD]], 0
-; CHECK-NEXT: [[PTR:%.*]] = select i1 [[CMP]], i16* [[A:%.*]], i16* [[B:%.*]]
+; CHECK-NEXT: [[PTR:%.*]] = select i1 [[CMP]], ptr [[A:%.*]], ptr [[B:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[SHR]] to i8
-; CHECK-NEXT: [[CALL:%.*]] = tail call zeroext i8 @do_something_with_ptr(i8 [[TMP3]], i16* [[PTR]])
+; CHECK-NEXT: [[CALL:%.*]] = tail call zeroext i8 @do_something_with_ptr(i8 [[TMP3]], ptr [[PTR]])
; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[CALL]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
; CHECK-NEXT: ret i8 [[TMP5]]
@@ -122,16 +122,16 @@ define i8 @call_pointer(i8 zeroext %x, i8 zeroext %y, i16* %a, i16* %b) {
%shr = lshr i8 %or, 1
%add = add nuw i8 %shr, 2
%cmp = icmp ne i8 %add, 0
- %ptr = select i1 %cmp, i16* %a, i16* %b
- %call = tail call zeroext i8 @do_something_with_ptr(i8 %shr, i16* %ptr)
+ %ptr = select i1 %cmp, ptr %a, ptr %b
+ %call = tail call zeroext i8 @do_something_with_ptr(i8 %shr, ptr %ptr)
ret i8 %call
}
-define i16 @pointer_to_pointer(i16** %arg, i16 zeroext %limit) {
+define i16 @pointer_to_pointer(ptr %arg, i16 zeroext %limit) {
; CHECK-LABEL: @pointer_to_pointer(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[ADDR:%.*]] = load i16*, i16** [[ARG:%.*]], align 8
-; CHECK-NEXT: [[VAL:%.*]] = load i16, i16* [[ADDR]], align 2
+; CHECK-NEXT: [[ADDR:%.*]] = load ptr, ptr [[ARG:%.*]], align 8
+; CHECK-NEXT: [[VAL:%.*]] = load i16, ptr [[ADDR]], align 2
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[VAL]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP0]], 7
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD]], 256
@@ -139,21 +139,20 @@ define i16 @pointer_to_pointer(i16** %arg, i16 zeroext %limit) {
; CHECK-NEXT: ret i16 [[RES]]
;
entry:
- %addr = load i16*, i16** %arg
- %val = load i16, i16* %addr
+ %addr = load ptr, ptr %arg
+ %val = load i16, ptr %addr
%add = add nuw i16 %val, 7
%cmp = icmp ult i16 %add, 256
%res = select i1 %cmp, i16 128, i16 255
ret i16 %res
}
-define i8 @gep_2d_array(i8** %a, i8 zeroext %arg) {
+define i8 @gep_2d_array(ptr %a, i8 zeroext %arg) {
; CHECK-LABEL: @gep_2d_array(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i8*, i8** [[A:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = load i8*, i8** [[ARRAYIDX_US]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32
; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 [[TMP3]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[SUB]], [[TMP0]]
@@ -161,16 +160,15 @@ define i8 @gep_2d_array(i8** %a, i8 zeroext %arg) {
; CHECK-NEXT: ret i8 [[RES]]
;
entry:
- %arrayidx.us = getelementptr inbounds i8*, i8** %a, i32 0
- %0 = load i8*, i8** %arrayidx.us, align 4
- %1 = load i8, i8* %0, align 1
+ %0 = load ptr, ptr %a, align 4
+ %1 = load i8, ptr %0, align 1
%sub = sub nuw i8 %1, 1
%cmp = icmp ult i8 %sub, %arg
%res = select i1 %cmp, i8 27, i8 54
ret i8 %res
}
-define void @gep_2d_array_loop(i16** nocapture readonly %a, i16** nocapture readonly %b, i32 %N) {
+define void @gep_2d_array_loop(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {
; CHECK-LABEL: @gep_2d_array_loop(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP30:%.*]] = icmp eq i32 [[N:%.*]], 0
@@ -180,20 +178,20 @@ define void @gep_2d_array_loop(i16** nocapture readonly %a, i16** nocapture read
; CHECK-NEXT: br label [[FOR_BODY4_US:%.*]]
; CHECK: for.body4.us:
; CHECK-NEXT: [[X_029_US:%.*]] = phi i32 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[INC_US:%.*]], [[FOR_BODY4_US]] ]
-; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i16*, i16** [[A:%.*]], i32 [[X_029_US]]
-; CHECK-NEXT: [[TMP0:%.*]] = load i16*, i16** [[ARRAYIDX_US]], align 4
-; CHECK-NEXT: [[ARRAYIDX5_US:%.*]] = getelementptr inbounds i16, i16* [[TMP0]], i32 [[Y_031_US]]
-; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* [[ARRAYIDX5_US]], align 2
+; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds ptr, ptr [[A:%.*]], i32 [[X_029_US]]
+; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX_US]], align 4
+; CHECK-NEXT: [[ARRAYIDX5_US:%.*]] = getelementptr inbounds i16, ptr [[TMP0]], i32 [[Y_031_US]]
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[ARRAYIDX5_US]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
; CHECK-NEXT: [[DEC_US:%.*]] = add nuw i32 [[TMP2]], 65535
; CHECK-NEXT: [[CMP6_US:%.*]] = icmp ult i32 [[DEC_US]], 16383
; CHECK-NEXT: [[SHL_US:%.*]] = shl nuw i32 [[DEC_US]], 2
; CHECK-NEXT: [[SPEC_SELECT_US:%.*]] = select i1 [[CMP6_US]], i32 [[SHL_US]], i32 [[DEC_US]]
-; CHECK-NEXT: [[ARRAYIDX10_US:%.*]] = getelementptr inbounds i16*, i16** [[B:%.*]], i32 [[X_029_US]]
-; CHECK-NEXT: [[TMP3:%.*]] = load i16*, i16** [[ARRAYIDX10_US]], align 4
-; CHECK-NEXT: [[ARRAYIDX11_US:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[Y_031_US]]
+; CHECK-NEXT: [[ARRAYIDX10_US:%.*]] = getelementptr inbounds ptr, ptr [[B:%.*]], i32 [[X_029_US]]
+; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARRAYIDX10_US]], align 4
+; CHECK-NEXT: [[ARRAYIDX11_US:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[Y_031_US]]
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[SPEC_SELECT_US]] to i16
-; CHECK-NEXT: store i16 [[TMP4]], i16* [[ARRAYIDX11_US]], align 2
+; CHECK-NEXT: store i16 [[TMP4]], ptr [[ARRAYIDX11_US]], align 2
; CHECK-NEXT: [[INC_US]] = add nuw i32 [[X_029_US]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC_US]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]], label [[FOR_BODY4_US]]
@@ -214,18 +212,18 @@ for.cond1.preheader.us:
for.body4.us:
%x.029.us = phi i32 [ 0, %for.cond1.preheader.us ], [ %inc.us, %for.body4.us ]
- %arrayidx.us = getelementptr inbounds i16*, i16** %a, i32 %x.029.us
- %0 = load i16*, i16** %arrayidx.us, align 4
- %arrayidx5.us = getelementptr inbounds i16, i16* %0, i32 %y.031.us
- %1 = load i16, i16* %arrayidx5.us, align 2
+ %arrayidx.us = getelementptr inbounds ptr, ptr %a, i32 %x.029.us
+ %0 = load ptr, ptr %arrayidx.us, align 4
+ %arrayidx5.us = getelementptr inbounds i16, ptr %0, i32 %y.031.us
+ %1 = load i16, ptr %arrayidx5.us, align 2
%dec.us = add nuw i16 %1, -1
%cmp6.us = icmp ult i16 %dec.us, 16383
%shl.us = shl nuw i16 %dec.us, 2
%spec.select.us = select i1 %cmp6.us, i16 %shl.us, i16 %dec.us
- %arrayidx10.us = getelementptr inbounds i16*, i16** %b, i32 %x.029.us
- %2 = load i16*, i16** %arrayidx10.us, align 4
- %arrayidx11.us = getelementptr inbounds i16, i16* %2, i32 %y.031.us
- store i16 %spec.select.us, i16* %arrayidx11.us, align 2
+ %arrayidx10.us = getelementptr inbounds ptr, ptr %b, i32 %x.029.us
+ %2 = load ptr, ptr %arrayidx10.us, align 4
+ %arrayidx11.us = getelementptr inbounds i16, ptr %2, i32 %y.031.us
+ store i16 %spec.select.us, ptr %arrayidx11.us, align 2
%inc.us = add nuw i32 %x.029.us, 1
%exitcond = icmp eq i32 %inc.us, %N
br i1 %exitcond, label %for.cond1.for.cond.cleanup3_crit_edge.us, label %for.body4.us
diff --git a/llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll b/llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll
index b664a8ed0453b..c6465615f9d32 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
-define i8 @eq_sgt(i8* %x, i8 *%y, i8 zeroext %z) {
+define i8 @eq_sgt(ptr %x, ptr %y, i8 zeroext %z) {
; CHECK-LABEL: @eq_sgt(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[LOAD0:%.*]] = load i8, i8* [[X:%.*]], align 1
-; CHECK-NEXT: [[LOAD1:%.*]] = load i8, i8* [[Y:%.*]], align 1
+; CHECK-NEXT: [[LOAD0:%.*]] = load i8, ptr [[X:%.*]], align 1
+; CHECK-NEXT: [[LOAD1:%.*]] = load i8, ptr [[Y:%.*]], align 1
; CHECK-NEXT: [[ADD:%.*]] = add i8 [[LOAD0]], [[Z:%.*]]
; CHECK-NEXT: [[SUB:%.*]] = sub i8 [[LOAD1]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[ADD]], -56
@@ -15,8 +15,8 @@ define i8 @eq_sgt(i8* %x, i8 *%y, i8 zeroext %z) {
; CHECK-NEXT: ret i8 [[RES1]]
;
entry:
- %load0 = load i8, i8* %x, align 1
- %load1 = load i8, i8* %y, align 1
+ %load0 = load i8, ptr %x, align 1
+ %load1 = load i8, ptr %y, align 1
%add = add i8 %load0, %z
%sub = sub i8 %load1, 1
%cmp = icmp eq i8 %add, 200
@@ -26,10 +26,10 @@ entry:
ret i8 %res1
}
-define i16 @ugt_slt(i16 *%x, i16 zeroext %y, i16 zeroext %z) {
+define i16 @ugt_slt(ptr %x, i16 zeroext %y, i16 zeroext %z) {
; CHECK-LABEL: @ugt_slt(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[LOAD0:%.*]] = load i16, i16* [[X:%.*]], align 1
+; CHECK-NEXT: [[LOAD0:%.*]] = load i16, ptr [[X:%.*]], align 1
; CHECK-NEXT: [[ADD:%.*]] = add i16 [[LOAD0]], [[Z:%.*]]
; CHECK-NEXT: [[SUB:%.*]] = sub i16 [[Y:%.*]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[ADD]], [[Z]]
@@ -39,7 +39,7 @@ define i16 @ugt_slt(i16 *%x, i16 zeroext %y, i16 zeroext %z) {
; CHECK-NEXT: ret i16 [[RES1]]
;
entry:
- %load0 = load i16, i16* %x, align 1
+ %load0 = load i16, ptr %x, align 1
%add = add i16 %load0, %z
%sub = sub i16 %y, 1
%cmp = icmp slt i16 %add, %z
@@ -49,11 +49,11 @@ entry:
ret i16 %res1
}
-define void @urem_trunc_icmps(i16** %in, i32* %g, i32* %k) {
+define void @urem_trunc_icmps(ptr %in, ptr %g, ptr %k) {
; CHECK-LABEL: @urem_trunc_icmps(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[PTR:%.*]] = load i16*, i16** [[IN:%.*]], align 4
-; CHECK-NEXT: [[LD:%.*]] = load i16, i16* [[PTR]], align 2
+; CHECK-NEXT: [[PTR:%.*]] = load ptr, ptr [[IN:%.*]], align 4
+; CHECK-NEXT: [[LD:%.*]] = load i16, ptr [[PTR]], align 2
; CHECK-NEXT: [[CMP_I:%.*]] = icmp eq i16 [[LD]], 0
; CHECK-NEXT: br i1 [[CMP_I]], label [[EXIT:%.*]], label [[COND_FALSE_I:%.*]]
; CHECK: cond.false.i:
@@ -64,8 +64,8 @@ define void @urem_trunc_icmps(i16** %in, i32* %g, i32* %k) {
; CHECK-NEXT: [[COND_IN_I_OFF0:%.*]] = phi i8 [ [[EXTRACT_T]], [[COND_FALSE_I]] ], [ [[ADD:%.*]], [[FOR_INC:%.*]] ]
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[COND_IN_I_OFF0]], 7
; CHECK-NEXT: [[CONV5:%.*]] = zext i1 [[CMP]] to i32
-; CHECK-NEXT: store i32 [[CONV5]], i32* [[G:%.*]], align 4
-; CHECK-NEXT: [[DOTPR:%.*]] = load i32, i32* [[K:%.*]], align 4
+; CHECK-NEXT: store i32 [[CONV5]], ptr [[G:%.*]], align 4
+; CHECK-NEXT: [[DOTPR:%.*]] = load i32, ptr [[K:%.*]], align 4
; CHECK-NEXT: [[TOBOOL13150:%.*]] = icmp eq i32 [[DOTPR]], 0
; CHECK-NEXT: br i1 [[TOBOOL13150]], label [[FOR_INC]], label [[EXIT]]
; CHECK: for.inc:
@@ -75,8 +75,8 @@ define void @urem_trunc_icmps(i16** %in, i32* %g, i32* %k) {
; CHECK-NEXT: ret void
;
entry:
- %ptr = load i16*, i16** %in, align 4
- %ld = load i16, i16* %ptr, align 2
+ %ptr = load ptr, ptr %in, align 4
+ %ld = load i16, ptr %ptr, align 2
%cmp.i = icmp eq i16 %ld, 0
br i1 %cmp.i, label %exit, label %cond.false.i
@@ -89,8 +89,8 @@ body:
%cond.in.i.off0 = phi i8 [ %extract.t, %cond.false.i ], [ %add, %for.inc ]
%cmp = icmp sgt i8 %cond.in.i.off0, 7
%conv5 = zext i1 %cmp to i32
- store i32 %conv5, i32* %g, align 4
- %.pr = load i32, i32* %k, align 4
+ store i32 %conv5, ptr %g, align 4
+ %.pr = load i32, ptr %k, align 4
%tobool13150 = icmp eq i32 %.pr, 0
br i1 %tobool13150, label %for.inc, label %exit
diff --git a/llvm/test/Transforms/TypePromotion/ARM/signed.ll b/llvm/test/Transforms/TypePromotion/ARM/signed.ll
index 7df8a305442e0..3890d01cc60db 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/signed.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/signed.ll
@@ -2,16 +2,16 @@
; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends.
-define i16 @test_signed_load(i16* %ptr) {
+define i16 @test_signed_load(ptr %ptr) {
; CHECK-LABEL: @test_signed_load(
-; CHECK-NEXT: [[LOAD:%.*]] = load i16, i16* [[PTR:%.*]], align 2
+; CHECK-NEXT: [[LOAD:%.*]] = load i16, ptr [[PTR:%.*]], align 2
; CHECK-NEXT: [[CONV0:%.*]] = zext i16 [[LOAD]] to i32
; CHECK-NEXT: [[CONV1:%.*]] = sext i16 [[LOAD]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CONV0]], [[CONV1]]
; CHECK-NEXT: [[CONV2:%.*]] = zext i1 [[CMP]] to i16
; CHECK-NEXT: ret i16 [[CONV2]]
;
- %load = load i16, i16* %ptr
+ %load = load i16, ptr %ptr
%conv0 = zext i16 %load to i32
%conv1 = sext i16 %load to i32
%cmp = icmp eq i32 %conv0, %conv1
@@ -59,11 +59,11 @@ define i16 @test_srem(i16 zeroext %arg) {
ret i16 %conv
}
-define i32 @test_signext_b(i8* %ptr, i8 signext %arg) {
+define i32 @test_signext_b(ptr %ptr, i8 signext %arg) {
; CHECK-LABEL: @test_signext_b(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = load i8, i8* [[PTR:%.*]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], [[TMP0]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP3]], 128
@@ -71,18 +71,18 @@ define i32 @test_signext_b(i8* %ptr, i8 signext %arg) {
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
- %0 = load i8, i8* %ptr, align 1
+ %0 = load i8, ptr %ptr, align 1
%1 = add nuw nsw i8 %0, %arg
%cmp = icmp ult i8 %1, 128
%res = select i1 %cmp, i32 42, i32 20894
ret i32 %res
}
-define i32 @test_signext_b_ult_slt(i8* %ptr, i8 signext %arg) {
+define i32 @test_signext_b_ult_slt(ptr %ptr, i8 signext %arg) {
; CHECK-LABEL: @test_signext_b_ult_slt(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = load i8, i8* [[PTR:%.*]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], [[TMP0]]
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8
@@ -93,7 +93,7 @@ define i32 @test_signext_b_ult_slt(i8* %ptr, i8 signext %arg) {
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
- %0 = load i8, i8* %ptr, align 1
+ %0 = load i8, ptr %ptr, align 1
%1 = add nuw nsw i8 %0, %arg
%cmp = icmp sle i8 %1, 126
%cmp.1 = icmp ule i8 %1, %arg
@@ -102,11 +102,11 @@ entry:
ret i32 %res
}
-define i32 @test_signext_h(i16* %ptr, i16 signext %arg) {
+define i32 @test_signext_h(ptr %ptr, i16 signext %arg) {
; CHECK-LABEL: @test_signext_h(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[ARG:%.*]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* [[PTR:%.*]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], [[TMP0]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP3]], 32768
@@ -114,7 +114,7 @@ define i32 @test_signext_h(i16* %ptr, i16 signext %arg) {
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
- %0 = load i16, i16* %ptr, align 1
+ %0 = load i16, ptr %ptr, align 1
%1 = add nuw nsw i16 %0, %arg
%cmp = icmp ult i16 %1, 32768
%res = select i1 %cmp, i32 42, i32 20894
diff --git a/llvm/test/Transforms/TypePromotion/ARM/switch.ll b/llvm/test/Transforms/TypePromotion/ARM/switch.ll
index 05ec5c02a8855..f91fc9411f826 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/switch.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/switch.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
-define void @truncate_source_phi_switch(i8* %memblock, i8* %store, i16 %arg) {
+define void @truncate_source_phi_switch(ptr %memblock, ptr %store, i16 %arg) {
; CHECK-LABEL: @truncate_source_phi_switch(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[PRE:%.*]] = load i8, i8* [[MEMBLOCK:%.*]], align 1
+; CHECK-NEXT: [[PRE:%.*]] = load i8, ptr [[MEMBLOCK:%.*]], align 1
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[PRE]] to i32
; CHECK-NEXT: [[CONV:%.*]] = trunc i16 [[ARG:%.*]] to i8
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[CONV]] to i32
@@ -31,13 +31,13 @@ define void @truncate_source_phi_switch(i8* %memblock, i8* %store, i16 %arg) {
; CHECK-NEXT: [[PHI_3]] = phi i32 [ [[XOR]], [[FOR_INC_I]] ], [ [[AND]], [[FOR_INC_I_I]] ], [ [[PHI_2]], [[DEFAULT]] ]
; CHECK-NEXT: [[COUNT]] = add nuw i32 [[PHI_2]], 1
; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[COUNT]] to i8
-; CHECK-NEXT: store i8 [[TMP2]], i8* [[STORE:%.*]], align 1
+; CHECK-NEXT: store i8 [[TMP2]], ptr [[STORE:%.*]], align 1
; CHECK-NEXT: br label [[HEADER]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
- %pre = load i8, i8* %memblock, align 1
+ %pre = load i8, ptr %memblock, align 1
%conv = trunc i16 %arg to i8
br label %header
@@ -66,7 +66,7 @@ default:
latch:
%phi.3 = phi i8 [ %xor, %for.inc.i ], [ %and, %for.inc.i.i ], [ %phi.2, %default ]
%count = add nuw i8 %phi.2, 1
- store i8 %count, i8* %store, align 1
+ store i8 %count, ptr %store, align 1
br label %header
exit:
@@ -235,16 +235,15 @@ exit:
%class.x = type { i8 }
%class.v = type { %class.q }
%class.q = type { i16 }
-declare %class.x* @_ZNK2ae2afEv(%class.ae*) local_unnamed_addr
-declare %class.v* @_ZN1x2acEv(%class.x*) local_unnamed_addr
+declare ptr @_ZNK2ae2afEv(ptr) local_unnamed_addr
+declare ptr @_ZN1x2acEv(ptr) local_unnamed_addr
-define i32 @trunc_i16_i9_switch(%class.ae* %this) {
+define i32 @trunc_i16_i9_switch(ptr %this) {
; CHECK-LABEL: @trunc_i16_i9_switch(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = tail call %class.x* @_ZNK2ae2afEv(%class.ae* [[THIS:%.*]])
-; CHECK-NEXT: [[CALL2:%.*]] = tail call %class.v* @_ZN1x2acEv(%class.x* [[CALL]])
-; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_V:%.*]], %class.v* [[CALL2]], i32 0, i32 0, i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2
+; CHECK-NEXT: [[CALL:%.*]] = tail call ptr @_ZNK2ae2afEv(ptr [[THIS:%.*]])
+; CHECK-NEXT: [[CALL2:%.*]] = tail call ptr @_ZN1x2acEv(ptr [[CALL]])
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[CALL2]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 511
; CHECK-NEXT: [[TRUNC:%.*]] = and i32 [[TMP3]], 448
@@ -265,20 +264,19 @@ define i32 @trunc_i16_i9_switch(%class.ae* %this) {
; CHECK-NEXT: ret i32 [[RETVAL_0]]
;
entry:
- %call = tail call %class.x* @_ZNK2ae2afEv(%class.ae* %this)
- %call2 = tail call %class.v* @_ZN1x2acEv(%class.x* %call)
- %0 = getelementptr inbounds %class.v, %class.v* %call2, i32 0, i32 0, i32 0
- %1 = load i16, i16* %0, align 2
- %2 = trunc i16 %1 to i9
- %trunc = and i9 %2, -64
+ %call = tail call ptr @_ZNK2ae2afEv(ptr %this)
+ %call2 = tail call ptr @_ZN1x2acEv(ptr %call)
+ %0 = load i16, ptr %call2, align 2
+ %1 = trunc i16 %0 to i9
+ %trunc = and i9 %1, -64
switch i9 %trunc, label %cleanup.fold.split [
i9 0, label %cleanup
i9 -256, label %if.then7
]
if.then7:
- %3 = and i16 %1, 7
- %tobool = icmp eq i16 %3, 0
+ %2 = and i16 %0, 7
+ %tobool = icmp eq i16 %2, 0
%cond = select i1 %tobool, i32 2, i32 1
br label %cleanup
diff --git a/llvm/test/Transforms/TypePromotion/ARM/wrapping.ll b/llvm/test/Transforms/TypePromotion/ARM/wrapping.ll
index fffcca8ffad59..377708cf71134 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/wrapping.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/wrapping.ll
@@ -213,10 +213,10 @@ define i32 @sext_sub_underflow_neg(i8 zeroext %a) {
ret i32 %res
}
-define i32 @safe_sub_imm_var(i8* %b) {
+define i32 @safe_sub_imm_var(ptr %b) {
; CHECK-LABEL: @safe_sub_imm_var(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[B:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[B:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 248, [[TMP1]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[SUB]], 252
@@ -224,17 +224,17 @@ define i32 @safe_sub_imm_var(i8* %b) {
; CHECK-NEXT: ret i32 [[CONV4]]
;
entry:
- %0 = load i8, i8* %b, align 1
+ %0 = load i8, ptr %b, align 1
%sub = sub nuw nsw i8 -8, %0
%cmp = icmp ugt i8 %sub, 252
%conv4 = zext i1 %cmp to i32
ret i32 %conv4
}
-define i32 @safe_sub_var_imm(i8* %b) {
+define i32 @safe_sub_var_imm(ptr %b) {
; CHECK-LABEL: @safe_sub_var_imm(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[B:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[B:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[TMP1]], 248
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[SUB]], 252
@@ -242,17 +242,17 @@ define i32 @safe_sub_var_imm(i8* %b) {
; CHECK-NEXT: ret i32 [[CONV4]]
;
entry:
- %0 = load i8, i8* %b, align 1
+ %0 = load i8, ptr %b, align 1
%sub = sub nuw nsw i8 %0, -8
%cmp = icmp ugt i8 %sub, 252
%conv4 = zext i1 %cmp to i32
ret i32 %conv4
}
-define i32 @safe_add_imm_var(i8* %b) {
+define i32 @safe_add_imm_var(ptr %b) {
; CHECK-LABEL: @safe_add_imm_var(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[B:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[B:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 129, [[TMP1]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[ADD]], 127
@@ -260,17 +260,17 @@ define i32 @safe_add_imm_var(i8* %b) {
; CHECK-NEXT: ret i32 [[CONV4]]
;
entry:
- %0 = load i8, i8* %b, align 1
+ %0 = load i8, ptr %b, align 1
%add = add nuw nsw i8 -127, %0
%cmp = icmp ugt i8 %add, 127
%conv4 = zext i1 %cmp to i32
ret i32 %conv4
}
-define i32 @safe_add_var_imm(i8* %b) {
+define i32 @safe_add_var_imm(ptr %b) {
; CHECK-LABEL: @safe_add_var_imm(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[B:%.*]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[B:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[TMP1]], 129
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[ADD]], 127
@@ -278,7 +278,7 @@ define i32 @safe_add_var_imm(i8* %b) {
; CHECK-NEXT: ret i32 [[CONV4]]
;
entry:
- %0 = load i8, i8* %b, align 1
+ %0 = load i8, ptr %b, align 1
%add = add nuw nsw i8 %0, -127
%cmp = icmp ugt i8 %add, 127
%conv4 = zext i1 %cmp to i32
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