[llvm] 6f7ff9b - [MC] Consistently use MCInstrDesc::getImplicitUses and getImplicitDefs. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 4 05:28:58 PST 2023
Author: Jay Foad
Date: 2023-01-04T13:16:12Z
New Revision: 6f7ff9b9336dac3936a23ad9fd8cfd1f86279128
URL: https://github.com/llvm/llvm-project/commit/6f7ff9b9336dac3936a23ad9fd8cfd1f86279128
DIFF: https://github.com/llvm/llvm-project/commit/6f7ff9b9336dac3936a23ad9fd8cfd1f86279128.diff
LOG: [MC] Consistently use MCInstrDesc::getImplicitUses and getImplicitDefs. NFC.
Added:
Modified:
llvm/include/llvm/MC/MCInstrDesc.h
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/lib/MC/MCInstrDesc.cpp
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/ARM/ARMFastISel.cpp
llvm/lib/Target/Hexagon/HexagonGenMux.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/X86/X86FastISel.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 120c3482ce708..f4dd4763a9426 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -599,7 +599,7 @@ class MCInstrDesc {
/// Return true if this instruction implicitly
/// uses the specified physical register.
bool hasImplicitUseOfPhysReg(unsigned Reg) const {
- if (const MCPhysReg *ImpUses = ImplicitUses)
+ if (const MCPhysReg *ImpUses = getImplicitUses())
for (; *ImpUses; ++ImpUses)
if (*ImpUses == Reg)
return true;
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index d63e48c73278d..56c5c58142388 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1393,11 +1393,11 @@ bool MIParser::verifyImplicitOperands(ArrayRef<ParsedMachineOperand> Operands,
// Gather all the expected implicit operands.
SmallVector<MachineOperand, 4> ImplicitOperands;
- if (MCID.ImplicitDefs)
+ if (MCID.getImplicitDefs())
for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
ImplicitOperands.push_back(
MachineOperand::CreateReg(*ImpDefs, true, true));
- if (MCID.ImplicitUses)
+ if (MCID.getImplicitUses())
for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
ImplicitOperands.push_back(
MachineOperand::CreateReg(*ImpUses, false, true));
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 53e67225705cc..11452436485b7 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -84,11 +84,11 @@ static void tryToGetTargetInfo(const MachineInstr &MI,
}
void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
- if (MCID->ImplicitDefs)
+ if (MCID->getImplicitDefs())
for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
++ImpDefs)
addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
- if (MCID->ImplicitUses)
+ if (MCID->getImplicitUses())
for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
++ImpUses)
addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index c84924a48b5a2..704c41b656b54 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1935,8 +1935,9 @@ Register FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
else {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addReg(Op0);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
@@ -1959,8 +1960,9 @@ Register FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addReg(Op0)
.addReg(Op1);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
@@ -1985,8 +1987,9 @@ Register FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
.addReg(Op0)
.addReg(Op1)
.addReg(Op2);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
@@ -2007,8 +2010,9 @@ Register FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addReg(Op0)
.addImm(Imm);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
@@ -2031,8 +2035,9 @@ Register FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
.addReg(Op0)
.addImm(Imm1)
.addImm(Imm2);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
@@ -2050,8 +2055,9 @@ Register FastISel::fastEmitInst_f(unsigned MachineInstOpcode,
else {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addFPImm(FPImm);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
@@ -2075,8 +2081,9 @@ Register FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
.addReg(Op0)
.addReg(Op1)
.addImm(Imm);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
@@ -2091,8 +2098,9 @@ Register FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
.addImm(Imm);
else {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II).addImm(Imm);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 3ac2a7bddc5ab..ac65ceed20ed7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -426,7 +426,8 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
NumRes = 1;
} else {
const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
- assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
+ assert(MCID.getImplicitDefs() &&
+ "Physical reg def must be in implicit def list!");
NumRes = MCID.getNumDefs();
for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
if (Reg == *ImpDef)
@@ -526,7 +527,7 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
if (!Node->isMachineOpcode())
continue;
const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
- if (!MCID.ImplicitDefs)
+ if (!MCID.getImplicitDefs())
continue;
for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index c573e3d4dfe6a..8c9ed303f2753 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1284,7 +1284,8 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
NumRes = 1;
} else {
const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
- assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
+ assert(MCID.getImplicitDefs() &&
+ "Physical reg def must be in implicit def list!");
NumRes = MCID.getNumDefs();
for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
if (Reg == *ImpDef)
@@ -1438,7 +1439,7 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {
CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
}
}
- if (!MCID.ImplicitDefs)
+ if (!MCID.getImplicitDefs())
continue;
for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
diff --git a/llvm/lib/MC/MCInstrDesc.cpp b/llvm/lib/MC/MCInstrDesc.cpp
index 49a4a2cb546a6..540acbbe66bde 100644
--- a/llvm/lib/MC/MCInstrDesc.cpp
+++ b/llvm/lib/MC/MCInstrDesc.cpp
@@ -31,7 +31,7 @@ bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
const MCRegisterInfo *MRI) const {
- if (const MCPhysReg *ImpDefs = ImplicitDefs)
+ if (const MCPhysReg *ImpDefs = getImplicitDefs())
for (; *ImpDefs; ++ImpDefs)
if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
return true;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index ed997c020ff9d..8acaf130c0885 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -3334,7 +3334,7 @@ unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
const unsigned Num = Desc.getNumImplicitUses();
for (unsigned i = 0; i < Num; ++i) {
- unsigned Reg = Desc.ImplicitUses[i];
+ unsigned Reg = Desc.getImplicitUses()[i];
switch (Reg) {
case AMDGPU::FLAT_SCR:
case AMDGPU::VCC:
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index a290903b5980a..77518e38ffef2 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -309,8 +309,8 @@ unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addReg(Op0));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg)
- .addReg(II.ImplicitDefs[0]));
+ TII.get(TargetOpcode::COPY), ResultReg)
+ .addReg(II.getImplicitDefs()[0]));
}
return ResultReg;
}
@@ -336,8 +336,8 @@ unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
.addReg(Op0)
.addReg(Op1));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg)
- .addReg(II.ImplicitDefs[0]));
+ TII.get(TargetOpcode::COPY), ResultReg)
+ .addReg(II.getImplicitDefs()[0]));
}
return ResultReg;
}
@@ -361,8 +361,8 @@ unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
.addReg(Op0)
.addImm(Imm));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg)
- .addReg(II.ImplicitDefs[0]));
+ TII.get(TargetOpcode::COPY), ResultReg)
+ .addReg(II.getImplicitDefs()[0]));
}
return ResultReg;
}
@@ -380,8 +380,8 @@ unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addImm(Imm));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg)
- .addReg(II.ImplicitDefs[0]));
+ TII.get(TargetOpcode::COPY), ResultReg)
+ .addReg(II.getImplicitDefs()[0]));
}
return ResultReg;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
index 55de02816fb8d..0b1429b7ee368 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -160,10 +160,10 @@ void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs,
// First, get the implicit defs and uses for this instruction.
unsigned Opc = MI->getOpcode();
const MCInstrDesc &D = HII->get(Opc);
- if (const MCPhysReg *R = D.ImplicitDefs)
+ if (const MCPhysReg *R = D.getImplicitDefs())
while (*R)
expandReg(*R++, Defs);
- if (const MCPhysReg *R = D.ImplicitUses)
+ if (const MCPhysReg *R = D.getImplicitUses())
while (*R)
expandReg(*R++, Uses);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index a5717c21f51fc..69875212a7cfe 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2741,13 +2741,13 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
const MCInstrDesc &NewDesc = get(NewOpC);
MI->setDesc(NewDesc);
- if (NewDesc.ImplicitDefs)
+ if (NewDesc.getImplicitDefs())
for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
*ImpDefs; ++ImpDefs)
if (!MI->definesRegister(*ImpDefs))
MI->addOperand(*MI->getParent()->getParent(),
MachineOperand::CreateReg(*ImpDefs, true, true));
- if (NewDesc.ImplicitUses)
+ if (NewDesc.getImplicitUses())
for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
*ImpUses; ++ImpUses)
if (!MI->readsRegister(*ImpUses))
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 6597e316cd9a6..d1313a9e35b40 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -3999,8 +3999,9 @@ unsigned X86FastISel::fastEmitInst_rrrr(unsigned MachineInstOpcode,
.addReg(Op1)
.addReg(Op2)
.addReg(Op3);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
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