[PATCH] D138814: [InstCombine] Combine a/lshr of add -> (a + b < a)

[Nikita Popov via Phabricator via llvm-commits]

nikic added inline comments.


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Comment at: llvm/test/Transforms/InstCombine/pr34349.ll:17
+; CHECK-NEXT:    [[ADD_NARROWED_OVERFLOW:%.*]] = icmp ult i7 [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[V14:%.*]] = zext i1 [[ADD_NARROWED_OVERFLOW]] to i8
 ; CHECK-NEXT:    ret i8 [[V14]]
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This case doesn't look like a profitable transform. Do I understand correctly that the actual motivating case here is the case where the inputs are `zext`, and then this was later generalized based on reviewer feedback to use known bits instead?

For the zext case, this looks like an obviously desirable transform, but for the general case (where the truncs may not fold away) this is less clearly beneficial. I would personally restrict this to just zext unless we have specific motivation otherwise. (But I'm also not going to fight this if reviewers disagree.)


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  https://reviews.llvm.org/D138814/new/

https://reviews.llvm.org/D138814