[PATCH] D140638: [Codegen][LegalizeIntegerTypes] New legalization strategy for scalar shifts: shift through stack

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 486115.
lebedev.ri added a comment.

Rebased.

In D140638#4024426 <https://reviews.llvm.org/D140638#4024426>, @efriedma wrote:

> A few header changes seem to be missing? I can't find a definition of ShiftLegalizationStrategy.
>
> It might be worth implementing a strategy that avoids unaligned loads (by splitting the shift amount by the native register width instead of CHAR_BIT).  On targets that don't have native unaligned loads, they're pretty expensive.  Even on targets that do have unaligned loads, an aligned load can reduce the cost of the store forwarding stall.  (But on targets with fast unaligned loads, they're probably worth using if the shift amount is known to be a multiple of CHAR_BIT.)

@efriedma thank you for taking a look!
Indeed, the fact that loads are unaligned has occurred to me.
But, this patch is already much bigger than i already planned.
Honestly, initially i only looked to handle `lshr` by multiple of `CHAR_BIT`,
and *everything* ontop of that just kinda kept being added.

I may be interested in looking into further follow-up improvements,
as long as the original patch (in general) does not result in really dragged our review,
but i really don't feel it's reasonable to do even more stuff here.
WDYT?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140638/new/

https://reviews.llvm.org/D140638

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/AArch64/wide-scalar-shift-by-byte-multiple-legalization.ll
  llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/AVR/shift.ll
  llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
  llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
  llvm/test/CodeGen/Mips/llvm-ir/shl.ll
  llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
  llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
  llvm/test/CodeGen/PowerPC/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
  llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/X86/scheduler-backtracking.ll
  llvm/test/CodeGen/X86/shift-i128.ll
  llvm/test/CodeGen/X86/shift-i256.ll
  llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
  llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
  llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll