[llvm] 7ff64d4 - [AMDGPU] Fix useDeprecatedPositionallyEncodedOperands errors.

[James Y Knight via llvm-commits]

Author: James Y Knight
Date: 2023-01-03T17:52:10-05:00
New Revision: 7ff64d44b9c10c77b60ffa4c7b1f6e58729475f3

URL: https://github.com/llvm/llvm-project/commit/7ff64d44b9c10c77b60ffa4c7b1f6e58729475f3
DIFF: https://github.com/llvm/llvm-project/commit/7ff64d44b9c10c77b60ffa4c7b1f6e58729475f3.diff

LOG: [AMDGPU] Fix useDeprecatedPositionallyEncodedOperands errors.

This is a follow-on to https://reviews.llvm.org/D134073.

The errors in the R600 half were fixed previously in
https://reviews.llvm.org/D134078. Originally, I thought that the fixes
to the AMDGPU half would be tricky, but upon taking another look,
there were only a couple minor issues that needed fixing:

1. Previously, buffer load instructions (`BUFFER_LOAD_*_LDS_*`) were
populating the `vdata` field in the instruction from the `swz`
operand. This was incorrect, but harmless, as when the LDS option is
set, the instruction does not use the vdata field.

2. The `BUFFER_STORE_LDS_DWORD_gfx90a` instruction was populating
`acc` from the `swz` operand, because `acc` was set to `?`. (I believe
that the intent here was to leave the instruction bit as an "unknown
value", but you can't do that except by setting the bits on `Inst`
directly). Also harmless, for the same reason.

Differential Revision: https://reviews.llvm.org/D140918

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPU.td
    llvm/lib/Target/AMDGPU/BUFInstructions.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index bc949964cdfeb..63861a1a90527 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1329,8 +1329,6 @@ def FeatureISAVersion11_0_3 : FeatureSet<
 
 def AMDGPUInstrInfo : InstrInfo {
   let guessInstructionProperties = 1;
-  let noNamedPositionallyEncodedOperands = 1;
-  let useDeprecatedPositionallyEncodedOperands = 1;
 }
 
 def AMDGPUAsmParser : AsmParser {

diff  --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 8891300e57528..08aa4e6d48247 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -337,7 +337,7 @@ class MUBUF_Real <MUBUF_Pseudo ps, string real_name = ps.Mnemonic> :
 
   // GFX90A+ only: instruction uses AccVGPR for data
   // Bit supersedes tfe.
-  bits<1> acc = !if(ps.has_vdata, vdata{9}, !if(ps.lds, ?, 0));
+  bits<1> acc = !if(ps.has_vdata, vdata{9}, 0);
 }
 
 // For cache invalidation instructions.
@@ -476,7 +476,7 @@ class MUBUF_Load_Pseudo <string opName,
 
   let Constraints = !if(HasTiedDest, "$vdata = $vdata_in", "");
   let LGKM_CNT = isLds;
-  let has_vdata = !not(isLdsOpc);
+  let has_vdata = !not(!or(isLds, isLdsOpc));
   let mayLoad = 1;
   let mayStore = isLds;
   let maybeAtomic = 1;