[llvm] 615333b - [TypePromotion] NewPM support.
Samuel Parker via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 3 07:12:44 PST 2023
Author: Samuel Parker
Date: 2023-01-03T15:09:29Z
New Revision: 615333bc09c42cdac4d69ea171e610cdcb06e803
URL: https://github.com/llvm/llvm-project/commit/615333bc09c42cdac4d69ea171e610cdcb06e803
DIFF: https://github.com/llvm/llvm-project/commit/615333bc09c42cdac4d69ea171e610cdcb06e803.diff
LOG: [TypePromotion] NewPM support.
Differential Revision: https://reviews.llvm.org/D140893
Added:
llvm/include/llvm/CodeGen/TypePromotion.h
Modified:
llvm/include/llvm/CodeGen/Passes.h
llvm/include/llvm/InitializePasses.h
llvm/lib/CodeGen/CMakeLists.txt
llvm/lib/CodeGen/CodeGen.cpp
llvm/lib/CodeGen/TypePromotion.cpp
llvm/lib/Passes/CMakeLists.txt
llvm/lib/Passes/PassBuilder.cpp
llvm/lib/Passes/PassRegistry.def
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/test/CodeGen/AArch64/bfis-in-loop.ll
llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll
llvm/test/Transforms/TypePromotion/AArch64/loops.ll
llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep2.ll
llvm/test/Transforms/TypePromotion/AArch64/search-loop.ll
llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll
llvm/test/Transforms/TypePromotion/AArch64/vla-zext.ll
llvm/test/Transforms/TypePromotion/ARM/calls.ll
llvm/test/Transforms/TypePromotion/ARM/casts.ll
llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll
llvm/test/Transforms/TypePromotion/ARM/icmps.ll
llvm/test/Transforms/TypePromotion/ARM/large-int.ll
llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep.ll
llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep2.ll
llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
llvm/test/Transforms/TypePromotion/ARM/pointers.ll
llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll
llvm/test/Transforms/TypePromotion/ARM/signed.ll
llvm/test/Transforms/TypePromotion/ARM/switch.ll
llvm/test/Transforms/TypePromotion/ARM/wrapping.ll
llvm/tools/opt/opt.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index 9dcdbd55b4d52..3f79ce379212d 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -535,7 +535,7 @@ namespace llvm {
FunctionPass *createPseudoProbeInserter();
/// Create IR Type Promotion pass. \see TypePromotion.cpp
- FunctionPass *createTypePromotionPass();
+ FunctionPass *createTypePromotionLegacyPass();
/// Add Flow Sensitive Discriminators. PassNum specifies the
/// sequence number of this pass (starting from 1).
diff --git a/llvm/include/llvm/CodeGen/TypePromotion.h b/llvm/include/llvm/CodeGen/TypePromotion.h
new file mode 100644
index 0000000000000..efe58232cdcdd
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/TypePromotion.h
@@ -0,0 +1,35 @@
+//===- TypePromotion.h ------------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// Defines an IR pass for type promotion.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_TYPEPROMOTION_H
+#define LLVM_CODEGEN_TYPEPROMOTION_H
+
+#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+
+class Function;
+class TargetMachine;
+
+class TypePromotionPass : public PassInfoMixin<TypePromotionPass> {
+private:
+ const TargetMachine *TM;
+
+public:
+ TypePromotionPass(const TargetMachine *TM): TM(TM) { }
+ PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+};
+
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_TYPEPROMOTION_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 2d6d43d5eceff..8af87e69b0258 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -402,7 +402,7 @@ void initializeTargetTransformInfoWrapperPassPass(PassRegistry&);
void initializeTLSVariableHoistLegacyPassPass(PassRegistry &);
void initializeTwoAddressInstructionPassPass(PassRegistry&);
void initializeTypeBasedAAWrapperPassPass(PassRegistry&);
-void initializeTypePromotionPass(PassRegistry&);
+void initializeTypePromotionLegacyPass(PassRegistry&);
void initializeUniformityInfoWrapperPassPass(PassRegistry &);
void initializeUnifyFunctionExitNodesLegacyPassPass(PassRegistry &);
void initializeUnifyLoopExitsLegacyPassPass(PassRegistry &);
diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt
index 9bd571af8b47d..275ee8019b14e 100644
--- a/llvm/lib/CodeGen/CMakeLists.txt
+++ b/llvm/lib/CodeGen/CMakeLists.txt
@@ -230,8 +230,8 @@ add_llvm_component_library(LLVMCodeGen
TargetRegisterInfo.cpp
TargetSchedule.cpp
TargetSubtargetInfo.cpp
- TypePromotion.cpp
TwoAddressInstructionPass.cpp
+ TypePromotion.cpp
UnreachableBlockElim.cpp
ValueTypes.cpp
VLIWMachineScheduler.cpp
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 32709091370f1..b1f080a2a9300 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -129,7 +129,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeTailDuplicatePass(Registry);
initializeTargetPassConfigPass(Registry);
initializeTwoAddressInstructionPassPass(Registry);
- initializeTypePromotionPass(Registry);
+ initializeTypePromotionLegacyPass(Registry);
initializeUnpackMachineBundlesPass(Registry);
initializeUnreachableBlockElimLegacyPassPass(Registry);
initializeUnreachableMachineBlockElimPass(Registry);
diff --git a/llvm/lib/CodeGen/TypePromotion.cpp b/llvm/lib/CodeGen/TypePromotion.cpp
index 5893c2cd5bc51..82ad80634277e 100644
--- a/llvm/lib/CodeGen/TypePromotion.cpp
+++ b/llvm/lib/CodeGen/TypePromotion.cpp
@@ -15,6 +15,7 @@
///
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/TypePromotion.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/LoopInfo.h"
@@ -133,7 +134,7 @@ class IRPromoter {
void Mutate();
};
-class TypePromotion : public FunctionPass {
+class TypePromotionImpl {
unsigned TypeSize = 0;
LLVMContext *Ctx = nullptr;
unsigned RegisterBitWidth = 0;
@@ -170,10 +171,16 @@ class TypePromotion : public FunctionPass {
bool isLegalToPromote(Value *V);
bool TryToPromote(Value *V, unsigned PromotedWidth, const LoopInfo &LI);
+public:
+ bool run(Function &F, const TargetMachine *TM,
+ const TargetTransformInfo &TTI, const LoopInfo &LI);
+};
+
+class TypePromotionLegacy : public FunctionPass {
public:
static char ID;
- TypePromotion() : FunctionPass(ID) {}
+ TypePromotionLegacy() : FunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<LoopInfoWrapperPass>();
@@ -196,19 +203,19 @@ static bool GenerateSignBits(Instruction *I) {
Opc == Instruction::SRem || Opc == Instruction::SExt;
}
-bool TypePromotion::EqualTypeSize(Value *V) {
+bool TypePromotionImpl::EqualTypeSize(Value *V) {
return V->getType()->getScalarSizeInBits() == TypeSize;
}
-bool TypePromotion::LessOrEqualTypeSize(Value *V) {
+bool TypePromotionImpl::LessOrEqualTypeSize(Value *V) {
return V->getType()->getScalarSizeInBits() <= TypeSize;
}
-bool TypePromotion::GreaterThanTypeSize(Value *V) {
+bool TypePromotionImpl::GreaterThanTypeSize(Value *V) {
return V->getType()->getScalarSizeInBits() > TypeSize;
}
-bool TypePromotion::LessThanTypeSize(Value *V) {
+bool TypePromotionImpl::LessThanTypeSize(Value *V) {
return V->getType()->getScalarSizeInBits() < TypeSize;
}
@@ -219,7 +226,7 @@ bool TypePromotion::LessThanTypeSize(Value *V) {
/// return values because we only accept ones that guarantee a zeroext ret val.
/// Many arguments will have the zeroext attribute too, so those would be free
/// too.
-bool TypePromotion::isSource(Value *V) {
+bool TypePromotionImpl::isSource(Value *V) {
if (!isa<IntegerType>(V->getType()))
return false;
@@ -240,7 +247,7 @@ bool TypePromotion::isSource(Value *V) {
/// Return true if V will require any promoted values to be truncated for the
/// the IR to remain valid. We can't mutate the value type of these
/// instructions.
-bool TypePromotion::isSink(Value *V) {
+bool TypePromotionImpl::isSink(Value *V) {
// TODO The truncate also isn't actually necessary because we would already
// proved that the data value is kept within the range of the original data
// type. We currently remove any truncs inserted for handling zext sinks.
@@ -266,7 +273,7 @@ bool TypePromotion::isSink(Value *V) {
}
/// Return whether this instruction can safely wrap.
-bool TypePromotion::isSafeWrap(Instruction *I) {
+bool TypePromotionImpl::isSafeWrap(Instruction *I) {
// We can support a potentially wrapping instruction (I) if:
// - It is only used by an unsigned icmp.
// - The icmp uses a constant.
@@ -372,7 +379,7 @@ bool TypePromotion::isSafeWrap(Instruction *I) {
return false;
}
-bool TypePromotion::shouldPromote(Value *V) {
+bool TypePromotionImpl::shouldPromote(Value *V) {
if (!isa<IntegerType>(V->getType()) || isSink(V))
return false;
@@ -683,7 +690,7 @@ void IRPromoter::Mutate() {
/// We disallow booleans to make life easier when dealing with icmps but allow
/// any other integer that fits in a scalar register. Void types are accepted
/// so we can handle switches.
-bool TypePromotion::isSupportedType(Value *V) {
+bool TypePromotionImpl::isSupportedType(Value *V) {
Type *Ty = V->getType();
// Allow voids and pointers, these won't be promoted.
@@ -701,7 +708,7 @@ bool TypePromotion::isSupportedType(Value *V) {
/// Disallow casts other than zext and truncs and only allow calls if their
/// return value is zeroext. We don't allow opcodes that can introduce sign
/// bits.
-bool TypePromotion::isSupportedValue(Value *V) {
+bool TypePromotionImpl::isSupportedValue(Value *V) {
if (auto *I = dyn_cast<Instruction>(V)) {
switch (I->getOpcode()) {
default:
@@ -749,7 +756,7 @@ bool TypePromotion::isSupportedValue(Value *V) {
/// Check that the type of V would be promoted and that the original type is
/// smaller than the targeted promoted type. Check that we're not trying to
/// promote something larger than our base 'TypeSize' type.
-bool TypePromotion::isLegalToPromote(Value *V) {
+bool TypePromotionImpl::isLegalToPromote(Value *V) {
auto *I = dyn_cast<Instruction>(V);
if (!I)
return true;
@@ -764,7 +771,7 @@ bool TypePromotion::isLegalToPromote(Value *V) {
return false;
}
-bool TypePromotion::TryToPromote(Value *V, unsigned PromotedWidth,
+bool TypePromotionImpl::TryToPromote(Value *V, unsigned PromotedWidth,
const LoopInfo &LI) {
Type *OrigTy = V->getType();
TypeSize = OrigTy->getPrimitiveSizeInBits().getFixedSize();
@@ -896,29 +903,23 @@ bool TypePromotion::TryToPromote(Value *V, unsigned PromotedWidth,
return true;
}
-bool TypePromotion::runOnFunction(Function &F) {
- if (skipFunction(F) || DisablePromotion)
+bool TypePromotionImpl::run(Function &F, const TargetMachine *TM,
+ const TargetTransformInfo &TTI,
+ const LoopInfo &LI) {
+ if (DisablePromotion)
return false;
LLVM_DEBUG(dbgs() << "IR Promotion: Running on " << F.getName() << "\n");
- auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
- if (!TPC)
- return false;
-
AllVisited.clear();
SafeToPromote.clear();
SafeWrap.clear();
bool MadeChange = false;
const DataLayout &DL = F.getParent()->getDataLayout();
- const TargetMachine &TM = TPC->getTM<TargetMachine>();
- const TargetSubtargetInfo *SubtargetInfo = TM.getSubtargetImpl(F);
+ const TargetSubtargetInfo *SubtargetInfo = TM->getSubtargetImpl(F);
const TargetLowering *TLI = SubtargetInfo->getTargetLowering();
- const TargetTransformInfo &TII =
- getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
- const LoopInfo &LI = getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
RegisterBitWidth =
- TII.getRegisterBitWidth(TargetTransformInfo::RGK_Scalar).getFixedSize();
+ TTI.getRegisterBitWidth(TargetTransformInfo::RGK_Scalar).getFixedSize();
Ctx = &F.getParent()->getContext();
// Return the preferred integer width of the instruction, or zero if we
@@ -1002,9 +1003,46 @@ bool TypePromotion::runOnFunction(Function &F) {
return MadeChange;
}
-INITIALIZE_PASS_BEGIN(TypePromotion, DEBUG_TYPE, PASS_NAME, false, false)
-INITIALIZE_PASS_END(TypePromotion, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS_BEGIN(TypePromotionLegacy, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
+INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
+INITIALIZE_PASS_END(TypePromotionLegacy, DEBUG_TYPE, PASS_NAME, false, false)
+
+char TypePromotionLegacy::ID = 0;
-char TypePromotion::ID = 0;
+bool TypePromotionLegacy::runOnFunction(Function &F) {
+ if (skipFunction(F))
+ return false;
-FunctionPass *llvm::createTypePromotionPass() { return new TypePromotion(); }
+ auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
+ if (!TPC)
+ return false;
+
+ auto *TM = &TPC->getTM<TargetMachine>();
+ auto &TTI = getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
+ auto &LI = getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
+
+ TypePromotionImpl TP;
+ return TP.run(F, TM, TTI, LI);
+}
+
+FunctionPass *llvm::createTypePromotionLegacyPass() {
+ return new TypePromotionLegacy();
+}
+
+PreservedAnalyses TypePromotionPass::run(Function &F,
+ FunctionAnalysisManager &AM) {
+ auto &TTI = AM.getResult<TargetIRAnalysis>(F);
+ auto &LI = AM.getResult<LoopAnalysis>(F);
+ TypePromotionImpl TP;
+
+ bool Changed = TP.run(F, TM, TTI, LI);
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA;
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<LoopAnalysis>();
+ return PA;
+}
diff --git a/llvm/lib/Passes/CMakeLists.txt b/llvm/lib/Passes/CMakeLists.txt
index c60706be266c4..576d0f3ff4429 100644
--- a/llvm/lib/Passes/CMakeLists.txt
+++ b/llvm/lib/Passes/CMakeLists.txt
@@ -16,6 +16,7 @@ add_llvm_component_library(LLVMPasses
LINK_COMPONENTS
AggressiveInstCombine
Analysis
+ CodeGen
Core
Coroutines
IPO
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index f9182eea98a54..9568f3ff139d8 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -72,6 +72,7 @@
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
#include "llvm/Analysis/UniformityAnalysis.h"
+#include "llvm/CodeGen/TypePromotion.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/PassManager.h"
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index 64824b76e59eb..edeae5b3db4a9 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -384,6 +384,7 @@ FUNCTION_PASS("speculative-execution", SpeculativeExecutionPass())
FUNCTION_PASS("strip-gc-relocates", StripGCRelocates())
FUNCTION_PASS("structurizecfg", StructurizeCFGPass())
FUNCTION_PASS("tailcallelim", TailCallElimPass())
+FUNCTION_PASS("typepromotion", TypePromotionPass(TM))
FUNCTION_PASS("unify-loop-exits", UnifyLoopExitsPass())
FUNCTION_PASS("vector-combine", VectorCombinePass())
FUNCTION_PASS("verify", VerifierPass())
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 1dabd558c9df6..eafd311c808ef 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -648,7 +648,7 @@ bool AArch64PassConfig::addPreISel() {
void AArch64PassConfig::addCodeGenPrepare() {
if (getOptLevel() != CodeGenOpt::None)
- addPass(createTypePromotionPass());
+ addPass(createTypePromotionLegacyPass());
TargetPassConfig::addCodeGenPrepare();
}
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 2d4fc636dee79..775d098fbaed5 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -456,7 +456,7 @@ void ARMPassConfig::addIRPasses() {
void ARMPassConfig::addCodeGenPrepare() {
if (getOptLevel() != CodeGenOpt::None)
- addPass(createTypePromotionPass());
+ addPass(createTypePromotionLegacyPass());
TargetPassConfig::addCodeGenPrepare();
}
diff --git a/llvm/test/CodeGen/AArch64/bfis-in-loop.ll b/llvm/test/CodeGen/AArch64/bfis-in-loop.ll
index 5f3879164b330..d139d12d4af04 100644
--- a/llvm/test/CodeGen/AArch64/bfis-in-loop.ll
+++ b/llvm/test/CodeGen/AArch64/bfis-in-loop.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: opt -mtriple=aarch64-linux-gnu -type-promotion < %s | llc -mtriple=aarch64-linux-gnu -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64-linux-gnu -passes=typepromotion < %s | llc -mtriple=aarch64-linux-gnu -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll b/llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll
index b77ffc041c924..65db6cabf9d2f 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/convert-utf.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -dce -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify,dce -S %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/loops.ll b/llvm/test/Transforms/TypePromotion/AArch64/loops.ll
index b341d87d5b1a6..07acd49d432fa 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/loops.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/loops.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify -S %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll b/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
index b24e4a10b69d1..96389f206f01d 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify -S %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep2.ll b/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep2.ll
index 4326580684edf..f969b7d72ece2 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep2.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify -S %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
; Function Attrs: mustprogress nofree nosync nounwind uwtable
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/search-loop.ll b/llvm/test/Transforms/TypePromotion/AArch64/search-loop.ll
index f51c033c23c16..5e9459152fb77 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/search-loop.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/search-loop.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -type-promotion -mtriple=aarch64 %s -o - | FileCheck %s
+; RUN: opt -S -passes=typepromotion -mtriple=aarch64 %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll b/llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll
index bcf8dfdd7cb0b..320e9bc5e5431 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/trunc-zext-chain.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64-linux-gnu -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64-linux-gnu -passes=typepromotion,verify -S %s -o - | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/Transforms/TypePromotion/AArch64/vla-zext.ll b/llvm/test/Transforms/TypePromotion/AArch64/vla-zext.ll
index 405c14e49c1c8..181e7d3c6aa4a 100644
--- a/llvm/test/Transforms/TypePromotion/AArch64/vla-zext.ll
+++ b/llvm/test/Transforms/TypePromotion/AArch64/vla-zext.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=aarch64 -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify -S %s -o - | FileCheck %s
define dso_local void @foo(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, ptr nocapture noundef writeonly %c, i64 noundef %n) local_unnamed_addr {
; CHECK-LABEL: @foo(
diff --git a/llvm/test/Transforms/TypePromotion/ARM/calls.ll b/llvm/test/Transforms/TypePromotion/ARM/calls.ll
index 8abaa0c6646e3..73efebda4a0ca 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/calls.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/calls.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
define i8 @call_with_imms(i8* %arg) {
; CHECK-LABEL: @call_with_imms(
diff --git a/llvm/test/Transforms/TypePromotion/ARM/casts.ll b/llvm/test/Transforms/TypePromotion/ARM/casts.ll
index 07469fe47e44d..80a4e178a34ca 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/casts.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/casts.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
define i16 @dsp_trunc(i32 %arg0, i32 %arg1, i16* %gep0, i16* %gep1) {
; CHECK-LABEL: @dsp_trunc(
diff --git a/llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll b/llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll
index 1735e736447d1..a8b8c411cb785 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/clear-structures.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
define i32 @clear_structures(i8* nocapture readonly %fmt, [1 x i32] %ap.coerce, i8* %out, void (i32, i8*)* nocapture %write) {
; CHECK-LABEL: @clear_structures(
diff --git a/llvm/test/Transforms/TypePromotion/ARM/icmps.ll b/llvm/test/Transforms/TypePromotion/ARM/icmps.ll
index cc744adb64118..ed179a033368e 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/icmps.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/icmps.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
define i32 @test_ult_254_inc_imm(i8 zeroext %x) {
; CHECK-LABEL: @test_ult_254_inc_imm(
diff --git a/llvm/test/Transforms/TypePromotion/ARM/large-int.ll b/llvm/test/Transforms/TypePromotion/ARM/large-int.ll
index 156eda086736d..b4ad05877b643 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/large-int.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/large-int.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=thumbv7 -type-promotion -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=thumbv7 -passes=typepromotion -S %s -o - | FileCheck %s
define hidden void @dont_promote_large_int(i8* %in, i64* %out) {
; CHECK-LABEL: @dont_promote_large_int(
diff --git a/llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep.ll b/llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep.ll
index 8b6b3094202de..c2bc55504e255 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
; Function Attrs: mustprogress nofree nosync nounwind uwtable
define dso_local void @foo(ptr noundef %ptr0, ptr nocapture noundef readonly %ptr1, ptr nocapture noundef %dest) local_unnamed_addr {
diff --git a/llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep2.ll b/llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep2.ll
index 8ee5dd00a8da0..4b5b0e5df9053 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep2.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/phi-zext-gep2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
; Function Attrs: mustprogress nofree nosync nounwind uwtable
define dso_local void @foo(ptr noundef %ptr0, ptr nocapture noundef readonly %ptr1, ptr nocapture noundef %dest) local_unnamed_addr {
diff --git a/llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll b/llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
index 116a2b2102c9c..004dc286628b0 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
; Check that the arguments are extended but then nothing else is.
; This also ensures that the pass can handle loops.
diff --git a/llvm/test/Transforms/TypePromotion/ARM/pointers.ll b/llvm/test/Transforms/TypePromotion/ARM/pointers.ll
index 3e37550186e69..4e81310505dd3 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/pointers.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/pointers.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
define void @phi_pointers(i16* %a, i16* %b, i8 zeroext %M, i8 zeroext %N) {
; CHECK-LABEL: @phi_pointers(
diff --git a/llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll b/llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll
index dfdd4c10ae87a..b664a8ed0453b 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/signed-icmps.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
define i8 @eq_sgt(i8* %x, i8 *%y, i8 zeroext %z) {
; CHECK-LABEL: @eq_sgt(
diff --git a/llvm/test/Transforms/TypePromotion/ARM/signed.ll b/llvm/test/Transforms/TypePromotion/ARM/signed.ll
index fb60a3f101f7d..7df8a305442e0 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/signed.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/signed.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends.
define i16 @test_signed_load(i16* %ptr) {
diff --git a/llvm/test/Transforms/TypePromotion/ARM/switch.ll b/llvm/test/Transforms/TypePromotion/ARM/switch.ll
index 6736ebeea4c43..05ec5c02a8855 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/switch.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/switch.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
define void @truncate_source_phi_switch(i8* %memblock, i8* %store, i16 %arg) {
; CHECK-LABEL: @truncate_source_phi_switch(
diff --git a/llvm/test/Transforms/TypePromotion/ARM/wrapping.ll b/llvm/test/Transforms/TypePromotion/ARM/wrapping.ll
index 1e5e3937c7f5d..fffcca8ffad59 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/wrapping.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/wrapping.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple=arm -type-promotion -verify -disable-type-promotion=false -S %s -o - | FileCheck %s
+; RUN: opt -mtriple=arm -passes=typepromotion,verify -S %s -o - | FileCheck %s
define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: @overflow_add(
diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp
index 6b756839e563d..4eb2c1e61d88e 100644
--- a/llvm/tools/opt/opt.cpp
+++ b/llvm/tools/opt/opt.cpp
@@ -373,7 +373,6 @@ static bool shouldPinPassToLegacyPM(StringRef Pass) {
"atomic-expand",
"expandvp",
"hardware-loops",
- "type-promotion",
"mve-tail-predication",
"interleaved-access",
"global-merge",
@@ -468,7 +467,6 @@ int main(int argc, char **argv) {
initializeWasmEHPreparePass(Registry);
initializeWriteBitcodePassPass(Registry);
initializeHardwareLoopsPass(Registry);
- initializeTypePromotionPass(Registry);
initializeReplaceWithVeclibLegacyPass(Registry);
initializeJMCInstrumenterPass(Registry);
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