[llvm] 6dd70c9 - Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-01-03T12:23:13Z
New Revision: 6dd70c9a4b3eae8085a2b4e2336ae8b72d87681f

URL: https://github.com/llvm/llvm-project/commit/6dd70c9a4b3eae8085a2b4e2336ae8b72d87681f
DIFF: https://github.com/llvm/llvm-project/commit/6dd70c9a4b3eae8085a2b4e2336ae8b72d87681f.diff

LOG: Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 6eb516762e492..a0d900c54e95b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -199,7 +199,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
     else
       return false;
 
-    if (Imm != 1 << (ShtAmt - 1))
+    if (Imm != 1ULL << (ShtAmt - 1))
       return false;
 
     Res1 = Op.getOperand(0);