[PATCH] D139609: [AArch64][DAGCombiner] fold instruction BIC from ISD::AND

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added a comment.

In D139609#4004201 <https://reviews.llvm.org/D139609#4004201>, @dmgreen wrote:

>> The headache thing here is DAGCombiner will revert the pattern to the origin if I use standard node. So I try to add a new AArch64ISD.
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>> Maybe I can put the transform to after legalize to make sure standard nodes exist longer.
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> Putting the transform late can certainly help, thats a good option if it is needed. It can sometimes be better to just prevent the DAG combine that is going in the wrong direction. There are a set of methods like shouldFoldConstantShiftPairToMask and isDesirableToCommuteWithShift that can be used by the target to control how the DAGCombiner acts. There can be problems if the transform is towards a canonical form that other DAG combines rely upon, but it sounds like in this case it might be easy enough to add?

These method like `shouldFoldConstantShiftPairToMask` or `isDesirableToCommuteWithShift` only prevent DAG to transform a good pattern to bad pattern for us. But if the code is the bad pattern at first, we still can't optimize the case. So if DAGCombiner already has some canonicalization, I prefer to optimize the pattern after DAG combine. And I am not sure if we need add a TLI interface, what interface can we add to make the code general?


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https://reviews.llvm.org/D139609