[PATCH] D140530: [RISCV] Add integer scalar instructions to isAssociativeAndCommutative

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

In D140530#4016511 <https://reviews.llvm.org/D140530#4016511>, @HsiangKai wrote:

> In D140530#4015004 <https://reviews.llvm.org/D140530#4015004>, @asi-sc wrote:
>
>> Have you had a chance to make some performance measurements?
>
> Quoted from D138107 <https://reviews.llvm.org/D138107>,
>
>   I run C/C++ benchmarks in SPECrate 2017 on Fujitsu A64FX processor, which has two pipelines for integer operations and SIMD/FP operations each. 511.povray_r had 4% improvement. Other benchmarks (int: 500, 502, 505, 520, 523, 525, 531, 541, 557; fp: 508, 510, 519, 538, 544) were within 1% up/down. For a synthetic benchmark, it doubled the performance.
>
> I have no performance number for RISC-V multiple issue machines. I am not sure what the impact is of the patch. Is there anyone can help to measure it?

By the way, the number from D138107 <https://reviews.llvm.org/D138107> are including SIMD/SVE instruction patterns. We only implement scalar part. (Vector instructions have more than 2 input operands. They are not applicable here.)


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