[llvm] 84ea726 - [NFC][DAG] `canCombineShuffleToAnyExtendVectorInreg()`: check for legal op before matching

Roman Lebedev via llvm-commits llvm-commits at lists.llvm.org
Sun Dec 25 14:47:56 PST 2022


Author: Roman Lebedev
Date: 2022-12-26T01:43:49+03:00
New Revision: 84ea72679e11f58378b9d5c9e2aaafb168b20bd8

URL: https://github.com/llvm/llvm-project/commit/84ea72679e11f58378b9d5c9e2aaafb168b20bd8
DIFF: https://github.com/llvm/llvm-project/commit/84ea72679e11f58378b9d5c9e2aaafb168b20bd8.diff

LOG: [NFC][DAG] `canCombineShuffleToAnyExtendVectorInreg()`: check for legal op before matching

Likewise as with legal types check, might as well not match if won't use.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8359cd8c9db8..2895cab84f44 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22619,13 +22619,11 @@ static std::optional<EVT> canCombineShuffleToAnyExtendVectorInreg(
     EVT OutSVT = EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits * Scale);
     EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale);
 
-    if (LegalTypes && !TLI.isTypeLegal(OutVT))
+    if ((LegalTypes && !TLI.isTypeLegal(OutVT)) ||
+        (LegalOperations && !TLI.isOperationLegalOrCustom(Opcode, OutVT)))
       continue;
 
-    if (!isAnyExtend(Scale))
-      continue;
-
-    if (!LegalOperations || TLI.isOperationLegalOrCustom(Opcode, OutVT))
+    if (isAnyExtend(Scale))
       return OutVT;
   }
 


        


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