[llvm] 6aa7359 - [NFC][DAG] `combineShuffleToVectorExtend()`: check that the type is legal first

[Roman Lebedev via llvm-commits]

Author: Roman Lebedev
Date: 2022-12-26T01:03:59+03:00
New Revision: 6aa735938782bbd35ba68fa5f3f04b717da674c7

URL: https://github.com/llvm/llvm-project/commit/6aa735938782bbd35ba68fa5f3f04b717da674c7
DIFF: https://github.com/llvm/llvm-project/commit/6aa735938782bbd35ba68fa5f3f04b717da674c7.diff

LOG: [NFC][DAG] `combineShuffleToVectorExtend()`: check that the type is legal first

There is no point in doing any of the potentially-costly matching
if we will inevitably give up anyway.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d4a03ec9af25..7b64fdd196f7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22619,19 +22619,21 @@ static SDValue combineShuffleToVectorExtend(ShuffleVectorSDNode *SVN,
     // Check for non power of 2 vector sizes
     if (NumElts % Scale != 0)
       continue;
-    if (!isAnyExtend(Scale))
-      continue;
 
     EVT OutSVT = EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits * Scale);
     EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale);
     // Never create an illegal type. Only create unsupported operations if we
     // are pre-legalization.
-    if (TLI.isTypeLegal(OutVT))
-      if (!LegalOperations ||
-          TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT))
-        return DAG.getBitcast(VT,
-                              DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG,
-                                          SDLoc(SVN), OutVT, N0));
+    if (!TLI.isTypeLegal(OutVT))
+      continue;
+
+    if (!isAnyExtend(Scale))
+      continue;
+
+    if (!LegalOperations ||
+        TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT))
+      return DAG.getBitcast(
+          VT, DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, SDLoc(SVN), OutVT, N0));
   }
 
   return SDValue();