[PATCH] D140659: Teach the AArch64 AdvSIMDScalarPass to support a more complete set of opcodes.

Owen Anderson via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Dec 24 22:52:47 PST 2022


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Refactor the pass modestly to support general N-operand instructions, not
just 3-operand.

The only significant category unsupported now is mul-add instructions.
These will require more extensive rework of the pass, since they have
tied operands.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140659

Files:
  llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
  llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll

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