[PATCH] D140638: [Codegen][LegalizeIntegerTypes] New legalization strategy for scalar shifts w/ shift amount by a multiple of CHAR_BIT

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 485200.
lebedev.ri edited the summary of this revision.
lebedev.ri added a comment.

Looks like i'm overengineering this.
The logic is even simpler: https://alive2.llvm.org/ce/z/YNVwd5
Instead of manually picking what goes into which half of stack slot, 
just extend+position the value that is being shifted, 
and just spill it. That allows the slot to be always filled in-order.

In D140638#4015850 <https://reviews.llvm.org/D140638#4015850>, @craig.topper wrote:

> In D140638#4015836 <https://reviews.llvm.org/D140638#4015836>, @lebedev.ri wrote:
>
>> Do conjure `MachinePointerInfo`.
>
> Isnt pointerinfo for stack automatically inferred?

Not for variable indexes into stack slot.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140638/new/

https://reviews.llvm.org/D140638

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/PowerPC/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
  llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll