[PATCH] D140649: [AArch64][SelectionDAG] Eliminates redundant zero-extension for 32-bit popcount

[Allen zhong via Phabricator via llvm-commits]

Allen created this revision.
Allen added reviewers: mingmingl, dmgreen, efriedma.
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Fix https://github.com/llvm/llvm-project/issues/59597.

      

Use SCALAR_TO_VECTOR to cast the scalar to vector as it is safe to
ignore the upper bits of the lowest lane, reference to D131047 <https://reviews.llvm.org/D131047>.


https://reviews.llvm.org/D140649

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-popcnt.ll
  llvm/test/CodeGen/AArch64/dp1.ll


Index: llvm/test/CodeGen/AArch64/dp1.ll
===================================================================
--- llvm/test/CodeGen/AArch64/dp1.ll
+++ llvm/test/CodeGen/AArch64/dp1.ll
@@ -202,7 +202,7 @@
 ; CHECK-SDAG-NEXT:    adrp x8, :got:var32
 ; CHECK-SDAG-NEXT:    ldr x8, [x8, :got_lo12:var32]
 ; CHECK-SDAG-NEXT:    ldr w9, [x8]
-; CHECK-SDAG-NEXT:    fmov d0, x9
+; CHECK-SDAG-NEXT:    fmov s0, w9
 ; CHECK-SDAG-NEXT:    cnt v0.8b, v0.8b
 ; CHECK-SDAG-NEXT:    uaddlv h0, v0.8b
 ; CHECK-SDAG-NEXT:    fmov w9, s0
Index: llvm/test/CodeGen/AArch64/arm64-popcnt.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-popcnt.ll
+++ llvm/test/CodeGen/AArch64/arm64-popcnt.ll
@@ -6,8 +6,7 @@
 define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
 ; CHECK-LABEL: cnt32_advsimd:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, w0
-; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    fmov s0, w0
 ; CHECK-NEXT:    cnt.8b v0, v0
 ; CHECK-NEXT:    uaddlv.8b h0, v0
 ; CHECK-NEXT:    fmov w0, s0
@@ -41,8 +40,6 @@
 ; CHECK-LABEL: cnt32_advsimd_2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fmov w8, s0
-; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    cnt.8b v0, v0
 ; CHECK-NEXT:    uaddlv.8b h0, v0
 ; CHECK-NEXT:    fmov w0, s0
@@ -267,6 +264,13 @@
 ; CHECK-NONEON-NEXT:    ccmp w0, #0, #4, eq
 ; CHECK-NONEON-NEXT:    cset w0, eq
 ; CHECK-NONEON-NEXT:    ret
+;
+; CHECK-CSSC-LABEL: ctpop32_ne_one:
+; CHECK-CSSC:       // %bb.0:
+; CHECK-CSSC-NEXT:    cnt w8, w0
+; CHECK-CSSC-NEXT:    cmp w8, #1
+; CHECK-CSSC-NEXT:    cset w0, ne
+; CHECK-CSSC-NEXT:    ret
   %count = tail call i32 @llvm.ctpop.i32(i32 %x)
   %cmp = icmp ne i32 %count, 1
   ret i1 %cmp
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8635,10 +8635,12 @@
   //  ADDV    B0, V0.8B     // sum 8xbyte pop-counts
   //  UMOV    X0, V0.B[0]   // copy byte result back to integer reg
   if (VT == MVT::i32 || VT == MVT::i64) {
+    // The inserted value(i32) cast them to the vector type
+    // by ignoring the upper bits of the lowest lane.
     if (VT == MVT::i32)
-      Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
-    Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
-
+      Val = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v8i8, Val);
+    else
+      Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
     SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
     SDValue UaddLV = DAG.getNode(
         ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,


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