[PATCH] D140638: [Codegen][LegalizeIntegerTypes] New legalization strategy for scalar shifts w/ shift amount by a multiple of CHAR_BIT

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:4165
+        DAG.getSetCC(dl, MVT::i1, Shiftee, AllZeros, ISD::SETLT);
+    Padding = DAG.getNode(ISD::SIGN_EXTEND, dl, VT, ShifteeIsNegative);
+  }
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craig.topper wrote:
> Can this be SRA of Shiftee by VTBits-1?
Right, i was not sure what should we emit here.
`SETCC` to `MVT::i1` is a bit questionable this late, so let's indeed go with `ashr`.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:4182
+  // NOTE: we can clamp to either VTByteWidth or VTByteWidth-1.
+  ByteOffset = DAG.getNode(ISD::UMIN, dl, ShAmtVT, ByteOffset,
+                           DAG.getConstant(VTByteWidth, dl, ShAmtVT));
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craig.topper wrote:
> Can this be clipped by masking with AND?
Right. I was just looking into that. We just need to call `clampDynamicVectorIndex()`.


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  https://reviews.llvm.org/D140638/new/

https://reviews.llvm.org/D140638