[PATCH] D140530: [RISCV] Add integer scalar instructions to isAssociativeAndCommutative
    Hsiangkai Wang via Phabricator via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Thu Dec 22 17:21:49 PST 2022
    
    
  
HsiangKai added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1375
+  case RISCV::MULW:
+  case RISCV::MULH:
+  case RISCV::MULHU:
----------------
craig.topper wrote:
> I don't think MULH and MULHU are associative.
I added them by mistake. Thanks for pointing it out.
Repository:
  rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140530/new/
https://reviews.llvm.org/D140530
    
    
More information about the llvm-commits
mailing list