[PATCH] D140493: [SROA] Support promotion in presence of variably-indexed loads

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

> @craig.topper i'm somewhat confused with that RISC-V codegen.
> The fact that it scalarizes *all* vector loads is a pretty glaring bug,
> which a bit disqualifies cost modelling question, since there are
> wider integer loads, that could be used instead. I'm rather not familiar
> with that target, so i'm not sure if i should look into it.

I haven't looked but I assume that's the type legalizer just doing SplitVector repeatedly and then doing ScalarizeVector. There is no intelligence for loads that are only used by stores.

NOTE: RISC-V also requires all scalar loads to be naturally aligned which can introduce additional restrictions on how a vector load/store can be scalarized.



> And after that, we are back to the question:
>
> is there support for shifts in base ISA?
> what is the widest integer type that can be shifted?

Yes there are shifts. riscv32 has 32-bit shifts. riscv64 has 64-bit shifts. smaller shifts need to promoted. wider shifts will be expanded. There is no cmov so expansion requires a select to be expanded to control flow.


Repository:
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  https://reviews.llvm.org/D140493/new/

https://reviews.llvm.org/D140493