[PATCH] D140573: [AVR] Optimize 32-bit shifts: optimize REG_SEQUENCE

[Ayke via Phabricator via llvm-commits]

aykevl created this revision.
aykevl added reviewers: benshi001, dylanmckay.
Herald added subscribers: Jim, hiraditya.
Herald added a project: All.
aykevl requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This pseudo-instruction stores two small (8-bit) registers into one wide (16-bit) register. But apparently the order matters a lot to the
register allocator.
This patch changes the order of inserting the registers to optimize for the best register allocation in the tests of shift32.ll. It might be detrimental in other cases, but keeping the registers in the same physical register seems like it would be a common case.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140573

Files:
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/test/CodeGen/AVR/shift32.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D140573.484910.patch
Type: text/x-patch
Size: 7722 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221222/39832984/attachment.bin>