[llvm] ac16ea8 - [SPARC] Fix SELECT_REG emission for f128s

[Brad Smith via llvm-commits]

Author: Koakuma
Date: 2022-12-22T13:52:56-05:00
New Revision: ac16ea89dbcfc362c6bef841ab543df08bf9e6ec

URL: https://github.com/llvm/llvm-project/commit/ac16ea89dbcfc362c6bef841ab543df08bf9e6ec
DIFF: https://github.com/llvm/llvm-project/commit/ac16ea89dbcfc362c6bef841ab543df08bf9e6ec.diff

LOG: [SPARC] Fix SELECT_REG emission for f128s

In LowerSELECT_CC, SELECT_REG between two f128s should only be emitted if we
have hardware quadfloat enabled.

This should fix issue #59646

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D140515

Added: 
    llvm/test/CodeGen/SPARC/fp128-select.ll

Modified: 
    llvm/lib/Target/Sparc/SparcISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index b1baf1e55e612..af678fd51a90c 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -2646,8 +2646,16 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
   if (LHS.getValueType().isInteger()) {
     // On V9 processors running in 64-bit mode, if CC compares two `i64`s
     // and the RHS is zero we might be able to use a specialized select.
+    // All SELECT_CC between any two scalar integer types are eligible for
+    // lowering to specialized instructions. Additionally, f32 and f64 types
+    // are also eligible, but for f128 we can only use the specialized
+    // instruction when we have hardquad.
+    EVT ValType = TrueVal.getValueType();
+    bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
+                          ValType == MVT::f64 ||
+                          (ValType == MVT::f128 && hasHardQuad);
     if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
-        isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC))
+        isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC) && IsEligibleType)
       return DAG.getNode(
           SPISD::SELECT_REG, dl, TrueVal.getValueType(), TrueVal, FalseVal,
           DAG.getConstant(intCondCCodeToRcond(CC), dl, MVT::i32), LHS);

diff  --git a/llvm/test/CodeGen/SPARC/fp128-select.ll b/llvm/test/CodeGen/SPARC/fp128-select.ll
new file mode 100644
index 0000000000000..72038e59b9fc8
--- /dev/null
+++ b/llvm/test/CodeGen/SPARC/fp128-select.ll
@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=sparcv9 -verify-machineinstrs < %s | FileCheck %s --check-prefix=V9
+
+define fp128 @f128_select_soft(fp128 %a, fp128 %b) #0 {
+; V9-LABEL: f128_select_soft:
+; V9:         .cfi_startproc
+; V9-NEXT:  ! %bb.0: ! %entry
+; V9-NEXT:    add %sp, -144, %sp
+; V9-NEXT:    .cfi_def_cfa_register %fp
+; V9-NEXT:    .cfi_window_save
+; V9-NEXT:    .cfi_register %o7, %i7
+; V9-NEXT:    add %sp, 2175, %o0
+; V9-NEXT:    or %o0, 8, %o0
+; V9-NEXT:    std %f6, [%o0]
+; V9-NEXT:    std %f4, [%sp+2175]
+; V9-NEXT:    ldx [%o0], %o0
+; V9-NEXT:    ldx [%sp+2175], %o1
+; V9-NEXT:    sethi 0, %o2
+; V9-NEXT:    or %o2, 0, %o2
+; V9-NEXT:    sethi 2097152, %o3
+; V9-NEXT:    or %o3, 0, %o3
+; V9-NEXT:    sllx %o3, 32, %o3
+; V9-NEXT:    or %o3, %o2, %o2
+; V9-NEXT:    xor %o1, %o2, %o1
+; V9-NEXT:    or %o0, %o1, %o0
+; V9-NEXT:    cmp %o0, 0
+; V9-NEXT:    bne %xcc, .LBB0_2
+; V9-NEXT:    nop
+; V9-NEXT:  ! %bb.1:
+; V9-NEXT:    sethi %h44(.LCPI0_0), %o0
+; V9-NEXT:    add %o0, %m44(.LCPI0_0), %o0
+; V9-NEXT:    sllx %o0, 12, %o0
+; V9-NEXT:    ldd [%o0+%l44(.LCPI0_0)], %f0
+; V9-NEXT:    add %o0, %l44(.LCPI0_0), %o0
+; V9-NEXT:    ldd [%o0+8], %f2
+; V9-NEXT:  .LBB0_2: ! %entry
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 144, %sp
+entry:
+  %0 = bitcast fp128 %b to i128
+  %xor.i = xor i128 %0, 0
+  %cmp19.i = icmp eq i128 %xor.i, -170141183460469231731687303715884105728
+  %spec.select277.i = select i1 %cmp19.i, fp128 0xL00000000000000007FFF800000000000, fp128 %a
+  ret fp128 %spec.select277.i
+}
+
+define fp128 @f128_select_hard(fp128 %a, fp128 %b) #1 {
+; V9-LABEL: f128_select_hard:
+; V9:         .cfi_startproc
+; V9-NEXT:  ! %bb.0: ! %entry
+; V9-NEXT:    add %sp, -144, %sp
+; V9-NEXT:    .cfi_def_cfa_register %fp
+; V9-NEXT:    .cfi_window_save
+; V9-NEXT:    .cfi_register %o7, %i7
+; V9-NEXT:    stq %f4, [%sp+2175]
+; V9-NEXT:    add %sp, 2175, %o0
+; V9-NEXT:    or %o0, 8, %o0
+; V9-NEXT:    ldx [%o0], %o0
+; V9-NEXT:    ldx [%sp+2175], %o1
+; V9-NEXT:    sethi 0, %o2
+; V9-NEXT:    or %o2, 0, %o2
+; V9-NEXT:    sethi %h44(.LCPI1_0), %o3
+; V9-NEXT:    add %o3, %m44(.LCPI1_0), %o3
+; V9-NEXT:    sllx %o3, 12, %o3
+; V9-NEXT:    ldq [%o3+%l44(.LCPI1_0)], %f4
+; V9-NEXT:    sethi 2097152, %o3
+; V9-NEXT:    or %o3, 0, %o3
+; V9-NEXT:    sllx %o3, 32, %o3
+; V9-NEXT:    or %o3, %o2, %o2
+; V9-NEXT:    xor %o1, %o2, %o1
+; V9-NEXT:    or %o0, %o1, %o0
+; V9-NEXT:    fmovrqz %o0, %f4, %f0
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 144, %sp
+entry:
+  %0 = bitcast fp128 %b to i128
+  %xor.i = xor i128 %0, 0
+  %cmp19.i = icmp eq i128 %xor.i, -170141183460469231731687303715884105728
+  %spec.select277.i = select i1 %cmp19.i, fp128 0xL00000000000000007FFF800000000000, fp128 %a
+  ret fp128 %spec.select277.i
+}
+
+attributes #0 = { "target-features"="-hard-quad-float" }
+attributes #1 = { "target-features"="+hard-quad-float" }