[PATCH] D140370: [VP][RISCV] Add vp.ctlz/cttz and RISC-V support.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:7441
+  case Intrinsic::vp_ctlz: {
+    bool IsZeroUndef = cast<ConstantInt>(VPIntrin.getArgOperand(3))->isZero();
+    ResOPC = IsZeroUndef ? ISD::VP_CTLZ : ISD::VP_CTLZ_ZERO_UNDEF;
----------------
The name of this variable is confusing. It's called IsZeroUndef but you select ISD::VP_CTLZ when the bool is true.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140370/new/

https://reviews.llvm.org/D140370