[PATCH] D140563: [SVE] Fix incorrect VT usage when lowering fixed length vector divides.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: psnobl, hiraditya, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: All.
paulwalker-arm requested review of this revision.
Herald added subscribers: llvm-commits, alextsao1999.
Herald added a project: LLVM.

Ensure the negation required when lowering negative power-of-two
divides uses the scalable vector container type with the fixed
length result extracted from it.

Fixes: #59647


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140563

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D140563.484868.patch
Type: text/x-patch
Size: 7298 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221222/abf2d7dc/attachment.bin>