[llvm] 20d72c4 - MIR: Don't assert if a virtual register uses a non-allocatable class

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-12-22T08:18:07-05:00
New Revision: 20d72c4917ce55cc9270a9ed48661a87edf311a6

URL: https://github.com/llvm/llvm-project/commit/20d72c4917ce55cc9270a9ed48661a87edf311a6
DIFF: https://github.com/llvm/llvm-project/commit/20d72c4917ce55cc9270a9ed48661a87edf311a6.diff

LOG: MIR: Don't assert if a virtual register uses a non-allocatable class

Added: 
    llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir

Modified: 
    llvm/lib/CodeGen/MIRParser/MIRParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index a19196e19cd46..1cc3cfa169400 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -659,9 +659,11 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
                                       const yaml::MachineFunction &YamlMF) {
   MachineFunction &MF = PFS.MF;
   MachineRegisterInfo &MRI = MF.getRegInfo();
+  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+
   bool Error = false;
   // Create VRegs
-  auto populateVRegInfo = [&] (const VRegInfo &Info, Twine Name) {
+  auto populateVRegInfo = [&](const VRegInfo &Info, Twine Name) {
     Register Reg = Info.VReg;
     switch (Info.Kind) {
     case VRegInfo::UNKNOWN:
@@ -670,6 +672,14 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
       Error = true;
       break;
     case VRegInfo::NORMAL:
+      if (!Info.D.RC->isAllocatable()) {
+        error(Twine("Cannot use non-allocatable class '") +
+              TRI->getRegClassName(Info.D.RC) + "' for virtual register " +
+              Name + " in function '" + MF.getName() + "'");
+        Error = true;
+        break;
+      }
+
       MRI.setRegClass(Reg, Info.D.RC);
       if (Info.PreferredReg != 0)
         MRI.setSimpleHint(Reg, Info.PreferredReg);
@@ -695,7 +705,6 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
   // Compute MachineRegisterInfo::UsedPhysRegMask
   for (const MachineBasicBlock &MBB : MF) {
     // Make sure MRI knows about registers clobbered by unwinder.
-    const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
     if (MBB.isEHPad())
       if (auto *RegMask = TRI->getCustomEHPadPreservedMask(MF))
         MRI.addPhysRegsUsedFromRegMask(RegMask);

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir
new file mode 100644
index 0000000000000..db149f9fb58eb
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir
@@ -0,0 +1,25 @@
+# RUN: not llc -mtriple=amdgcn-- -mcpu=gfx900 -run-pass=none -o - %s 2>&1 | FileCheck %s
+
+# Check a diagnostic is emitted if non-allocatable classes are used
+# with virtual registers, and there's no assert.
+
+# CHECK: error: {{.*}}: Cannot determine use non-allocatable class 'TTMP_32' for virtual register named_use in function 'virtreg_unallocatable'
+# CHECK: error: {{.*}}: Cannot determine use non-allocatable class 'TTMP_32' for virtual register named_def in function 'virtreg_unallocatable'
+# CHECK: error: {{.*}}: Cannot determine use non-allocatable class 'TTMP_32' for virtual register 0 in function 'virtreg_unallocatable'
+# CHECK: error: {{.*}}: Cannot determine use non-allocatable class 'TTMP_32' for virtual register 2 in function 'virtreg_unallocatable'
+# CHECK: error: {{.*}}: Cannot determine use non-allocatable class 'TTMP_32' for virtual register 1 in function 'virtreg_unallocatable'
+
+---
+name: virtreg_unallocatable
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: ttmp_32}
+body:             |
+  bb.0:
+    %1:ttmp_32 = IMPLICIT_DEF
+    S_NOP 0, implicit %2:ttmp_32
+
+    %named_def:ttmp_32 = IMPLICIT_DEF
+    S_NOP 0, implicit %named_use:ttmp_32
+
+...