[PATCH] D140515: [SPARC] Fix SELECT_REG emission for f128s

[Koakuma via Phabricator via llvm-commits]

koakuma added inline comments.


================
Comment at: llvm/lib/Target/Sparc/SparcISelLowering.cpp:2652
+        isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC) &&
+        (hasHardQuad || TrueVal.getValueType() != MVT::f128))
       return DAG.getNode(
----------------
arsenm wrote:
> koakuma wrote:
> > arsenm wrote:
> > > Could you check isTypeLegal instead?
> > I don't think that I could use isTypeLegal here?
> > Disabling hardquad only turns off the instructions, but the registers are still there (this is because the ISA defines an f128 register to be simply a group of four f32 registers), so isTypeLegal(f128) will always return true regardless of whether we have hardquad instructions or not.
> Is there another affirmative way to express the condition?
The most I can think is adding another `if` inside it like so:
```
if (is64Bit && ...) {
  if (TrueVal.getValueType() == MVT::f128 && !hasHardQuad) {
    // do nothing
  } else {
    return ...
  }
}
```
Would this be okay?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140515/new/

https://reviews.llvm.org/D140515