[PATCH] D140515: [SPARC] Fix SELECT_REG emission for f128s

[Koakuma via Phabricator via llvm-commits]

koakuma created this revision.
koakuma added reviewers: ro, arsenm, MaskRay, dcederman, brad.
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Herald added subscribers: llvm-commits, wdng.
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In LowerSELECT_CC, SELECT_REG between two f128s should only be emitted if we have hardware quadfloat enabled.

This should fix issue #59646 (https://github.com/llvm/llvm-project/issues/59646).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140515

Files:
  llvm/lib/Target/Sparc/SparcISelLowering.cpp
  llvm/test/CodeGen/SPARC/fp128-select.ll


Index: llvm/test/CodeGen/SPARC/fp128-select.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/SPARC/fp128-select.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=sparcv9 -verify-machineinstrs < %s | FileCheck %s --check-prefix=V9
+
+define fp128 @f128_select(fp128 %a, fp128 %b) {
+; V9-LABEL: f128_select:
+; V9:         .cfi_startproc
+; V9-NEXT:  ! %bb.0: ! %entry
+; V9-NEXT:    add %sp, -144, %sp
+; V9-NEXT:    .cfi_def_cfa_register %fp
+; V9-NEXT:    .cfi_window_save
+; V9-NEXT:    .cfi_register %o7, %i7
+; V9-NEXT:    add %sp, 2175, %o0
+; V9-NEXT:    or %o0, 8, %o0
+; V9-NEXT:    std %f6, [%o0]
+; V9-NEXT:    std %f4, [%sp+2175]
+; V9-NEXT:    ldx [%o0], %o0
+; V9-NEXT:    ldx [%sp+2175], %o1
+; V9-NEXT:    sethi 0, %o2
+; V9-NEXT:    or %o2, 0, %o2
+; V9-NEXT:    sethi 2097152, %o3
+; V9-NEXT:    or %o3, 0, %o3
+; V9-NEXT:    sllx %o3, 32, %o3
+; V9-NEXT:    or %o3, %o2, %o2
+; V9-NEXT:    xor %o1, %o2, %o1
+; V9-NEXT:    or %o0, %o1, %o0
+; V9-NEXT:    cmp %o0, 0
+; V9-NEXT:    bne %xcc, .LBB0_2
+; V9-NEXT:    nop
+; V9-NEXT:  ! %bb.1:
+; V9-NEXT:    sethi %h44(.LCPI0_0), %o0
+; V9-NEXT:    add %o0, %m44(.LCPI0_0), %o0
+; V9-NEXT:    sllx %o0, 12, %o0
+; V9-NEXT:    ldd [%o0+%l44(.LCPI0_0)], %f0
+; V9-NEXT:    add %o0, %l44(.LCPI0_0), %o0
+; V9-NEXT:    ldd [%o0+8], %f2
+; V9-NEXT:  .LBB0_2: ! %entry
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 144, %sp
+entry:
+  %0 = bitcast fp128 %b to i128
+  %xor.i = xor i128 %0, 0
+  %cmp19.i = icmp eq i128 %xor.i, -170141183460469231731687303715884105728
+  %spec.select277.i = select i1 %cmp19.i, fp128 0xL00000000000000007FFF800000000000, fp128 %a
+  ret fp128 %spec.select277.i
+}
Index: llvm/lib/Target/Sparc/SparcISelLowering.cpp
===================================================================
--- llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -2641,13 +2641,15 @@
   // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
   LookThroughSetCC(LHS, RHS, CC, SPCC);
   assert(LHS.getValueType() == RHS.getValueType());
+  assert(TrueVal.getValueType() == FalseVal.getValueType());
 
   SDValue CompareFlag;
   if (LHS.getValueType().isInteger()) {
     // On V9 processors running in 64-bit mode, if CC compares two `i64`s
     // and the RHS is zero we might be able to use a specialized select.
     if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
-        isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC))
+        isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC) &&
+        (hasHardQuad || TrueVal.getValueType() != MVT::f128))
       return DAG.getNode(
           SPISD::SELECT_REG, dl, TrueVal.getValueType(), TrueVal, FalseVal,
           DAG.getConstant(intCondCCodeToRcond(CC), dl, MVT::i32), LHS);


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