[llvm] 9b227cb - [RISCV] Check the sign bits of the input of RISCVISD::ABSW in computeNumSignBitsForTargetNode.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-12-21T12:56:35-08:00
New Revision: 9b227cb1f536829ce109f7334beceb71f804d58b

URL: https://github.com/llvm/llvm-project/commit/9b227cb1f536829ce109f7334beceb71f804d58b
DIFF: https://github.com/llvm/llvm-project/commit/9b227cb1f536829ce109f7334beceb71f804d58b.diff

LOG: [RISCV] Check the sign bits of the input of RISCVISD::ABSW in computeNumSignBitsForTargetNode.

We created a SIGN_EXTEND_INREG when we created the ABSW so the
input should have 33 sign bits, but check it to be safe.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d34786d5d0fdd..7deccd8e76105 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10511,6 +10511,14 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
         DAG.ComputeNumSignBits(Op.getOperand(4), DemandedElts, Depth + 1);
     return std::min(Tmp, Tmp2);
   }
+  case RISCVISD::ABSW: {
+    // We expand this at isel to negw+max. The result will have 33 sign bits
+    // if the input has at least 33 sign bits.
+    unsigned Tmp =
+        DAG.ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
+    if (Tmp < 33) return 1;
+    return 33;
+  }
   case RISCVISD::SLLW:
   case RISCVISD::SRAW:
   case RISCVISD::SRLW:
@@ -10519,7 +10527,6 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
   case RISCVISD::REMUW:
   case RISCVISD::ROLW:
   case RISCVISD::RORW:
-  case RISCVISD::ABSW:
   case RISCVISD::FCVT_W_RV64:
   case RISCVISD::FCVT_WU_RV64:
   case RISCVISD::STRICT_FCVT_W_RV64: