[llvm] cd7428c - [NFC][SROA] Add tests for alloca promotion in presence of variably-indexed load
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 21 12:17:23 PST 2022
Author: Roman Lebedev
Date: 2022-12-21T23:16:50+03:00
New Revision: cd7428cac7b5c47d5399e8ea9926844eb711f1a6
URL: https://github.com/llvm/llvm-project/commit/cd7428cac7b5c47d5399e8ea9926844eb711f1a6
DIFF: https://github.com/llvm/llvm-project/commit/cd7428cac7b5c47d5399e8ea9926844eb711f1a6.diff
LOG: [NFC][SROA] Add tests for alloca promotion in presence of variably-indexed load
Added:
llvm/test/Transforms/SROA/widen-load-of-small-alloca.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SROA/widen-load-of-small-alloca.ll b/llvm/test/Transforms/SROA/widen-load-of-small-alloca.ll
new file mode 100644
index 0000000000000..4e532b9ea72bd
--- /dev/null
+++ b/llvm/test/Transforms/SROA/widen-load-of-small-alloca.ll
@@ -0,0 +1,505 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes='sroa<preserve-cfg>' -data-layout="e-n8:16:32:64" -S %s | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-SCALAR,CHECK-SCALAR-64,CHECK-LE-64
+; RUN: opt -passes='sroa<modify-cfg>' -data-layout="e-n8:16:32:64" -S %s | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-SCALAR,CHECK-SCALAR-64,CHECK-LE-64
+; RUN: opt -passes='sroa<preserve-cfg>' -data-layout="e-n8:16:32" -S %s | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-SCALAR,CHECK-SCALAR-32,CHECK-LE-32
+; RUN: opt -passes='sroa<modify-cfg>' -data-layout="e-n8:16:32" -S %s | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-SCALAR,CHECK-SCALAR-32,CHECK-LE-32
+; RUN: opt -passes='sroa<preserve-cfg>' -data-layout="E-n8:16:32:64" -S %s | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-SCALAR,CHECK-SCALAR-64,CHECK-BE-64
+; RUN: opt -passes='sroa<modify-cfg>' -data-layout="E-n8:16:32:64" -S %s | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-SCALAR,CHECK-SCALAR-64,CHECK-BE-64
+; RUN: opt -passes='sroa<preserve-cfg>' -data-layout="E-n8:16:32" -S %s | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-SCALAR,CHECK-SCALAR-32,CHECK-BE-32
+; RUN: opt -passes='sroa<modify-cfg>' -data-layout="E-n8:16:32" -S %s | FileCheck %s --check-prefixes=CHECK-ALL,CHECK-SCALAR,CHECK-SCALAR-32,CHECK-BE-32
+
+define void @load-1byte-chunk-of-1byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-1byte-chunk-of-1byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [1 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <1 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <1 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <1 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v1i8(<1 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [1 x i8], align 64
+ %init = load <1 x i8>, ptr %src, align 1
+ store <1 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <1 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v1i8(<1 x i8> %chunk)
+ ret void
+}
+
+define void @load-1byte-chunk-of-2byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-1byte-chunk-of-2byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [2 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <2 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <2 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <1 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v1i8(<1 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [2 x i8], align 64
+ %init = load <2 x i8>, ptr %src, align 1
+ store <2 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <1 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v1i8(<1 x i8> %chunk)
+ ret void
+}
+
+define void @load-2byte-chunk-of-2byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-2byte-chunk-of-2byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [2 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <2 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <2 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <2 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v2i8(<2 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [2 x i8], align 64
+ %init = load <2 x i8>, ptr %src, align 1
+ store <2 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <2 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v2i8(<2 x i8> %chunk)
+ ret void
+}
+
+define void @load-1byte-chunk-of-4byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-1byte-chunk-of-4byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [4 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <4 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <4 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <1 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v1i8(<1 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [4 x i8], align 64
+ %init = load <4 x i8>, ptr %src, align 1
+ store <4 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <1 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v1i8(<1 x i8> %chunk)
+ ret void
+}
+
+define void @load-2byte-chunk-of-4byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-2byte-chunk-of-4byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [4 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <4 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <4 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <2 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v2i8(<2 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [4 x i8], align 64
+ %init = load <4 x i8>, ptr %src, align 1
+ store <4 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <2 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v2i8(<2 x i8> %chunk)
+ ret void
+}
+
+define void @load-4byte-chunk-of-4byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-4byte-chunk-of-4byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [4 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <4 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <4 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <4 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v4i8(<4 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [4 x i8], align 64
+ %init = load <4 x i8>, ptr %src, align 1
+ store <4 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <4 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v4i8(<4 x i8> %chunk)
+ ret void
+}
+
+define void @load-1byte-chunk-of-8byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-1byte-chunk-of-8byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [8 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <8 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <8 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <1 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v1i8(<1 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [8 x i8], align 64
+ %init = load <8 x i8>, ptr %src, align 1
+ store <8 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <1 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v1i8(<1 x i8> %chunk)
+ ret void
+}
+
+define void @load-2byte-chunk-of-8byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-2byte-chunk-of-8byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [8 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <8 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <8 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <2 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v2i8(<2 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [8 x i8], align 64
+ %init = load <8 x i8>, ptr %src, align 1
+ store <8 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <2 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v2i8(<2 x i8> %chunk)
+ ret void
+}
+
+define void @load-4byte-chunk-of-8byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-4byte-chunk-of-8byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [8 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <8 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <8 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <4 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v4i8(<4 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [8 x i8], align 64
+ %init = load <8 x i8>, ptr %src, align 1
+ store <8 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <4 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v4i8(<4 x i8> %chunk)
+ ret void
+}
+
+define void @load-8byte-chunk-of-8byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-8byte-chunk-of-8byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [8 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <8 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <8 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <8 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v8i8(<8 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [8 x i8], align 64
+ %init = load <8 x i8>, ptr %src, align 1
+ store <8 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <8 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v8i8(<8 x i8> %chunk)
+ ret void
+}
+
+define void @load-1byte-chunk-of-16byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-1byte-chunk-of-16byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [16 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <16 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <16 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <1 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v1i8(<1 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [16 x i8], align 64
+ %init = load <16 x i8>, ptr %src, align 1
+ store <16 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <1 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v1i8(<1 x i8> %chunk)
+ ret void
+}
+
+define void @load-2byte-chunk-of-16byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-2byte-chunk-of-16byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [16 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <16 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <16 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <2 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v2i8(<2 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [16 x i8], align 64
+ %init = load <16 x i8>, ptr %src, align 1
+ store <16 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <2 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v2i8(<2 x i8> %chunk)
+ ret void
+}
+
+define void @load-4byte-chunk-of-16byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-4byte-chunk-of-16byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [16 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <16 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <16 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <4 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v4i8(<4 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [16 x i8], align 64
+ %init = load <16 x i8>, ptr %src, align 1
+ store <16 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <4 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v4i8(<4 x i8> %chunk)
+ ret void
+}
+
+define void @load-8byte-chunk-of-16byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-8byte-chunk-of-16byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [16 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <16 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <16 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <8 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v8i8(<8 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [16 x i8], align 64
+ %init = load <16 x i8>, ptr %src, align 1
+ store <16 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <8 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v8i8(<8 x i8> %chunk)
+ ret void
+}
+
+define void @load-16byte-chunk-of-16byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-16byte-chunk-of-16byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [16 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <16 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <16 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <16 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v16i8(<16 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [16 x i8], align 64
+ %init = load <16 x i8>, ptr %src, align 1
+ store <16 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <16 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v16i8(<16 x i8> %chunk)
+ ret void
+}
+
+define void @load-1byte-chunk-of-32byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-1byte-chunk-of-32byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [32 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <32 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <32 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <1 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v1i8(<1 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [32 x i8], align 64
+ %init = load <32 x i8>, ptr %src, align 1
+ store <32 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <1 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v1i8(<1 x i8> %chunk)
+ ret void
+}
+
+define void @load-2byte-chunk-of-32byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-2byte-chunk-of-32byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [32 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <32 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <32 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <2 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v2i8(<2 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [32 x i8], align 64
+ %init = load <32 x i8>, ptr %src, align 1
+ store <32 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <2 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v2i8(<2 x i8> %chunk)
+ ret void
+}
+
+define void @load-4byte-chunk-of-32byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-4byte-chunk-of-32byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [32 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <32 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <32 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <4 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v4i8(<4 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [32 x i8], align 64
+ %init = load <32 x i8>, ptr %src, align 1
+ store <32 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <4 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v4i8(<4 x i8> %chunk)
+ ret void
+}
+
+define void @load-8byte-chunk-of-32byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-8byte-chunk-of-32byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [32 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <32 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <32 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <8 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v8i8(<8 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [32 x i8], align 64
+ %init = load <32 x i8>, ptr %src, align 1
+ store <32 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <8 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v8i8(<8 x i8> %chunk)
+ ret void
+}
+
+define void @load-16byte-chunk-of-32byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-16byte-chunk-of-32byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [32 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <32 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <32 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <16 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v16i8(<16 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [32 x i8], align 64
+ %init = load <32 x i8>, ptr %src, align 1
+ store <32 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <16 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v16i8(<16 x i8> %chunk)
+ ret void
+}
+
+define void @load-32byte-chunk-of-32byte-alloca(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-32byte-chunk-of-32byte-alloca(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [32 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <32 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <32 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i8, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <32 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v32i8(<32 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [32 x i8], align 64
+ %init = load <32 x i8>, ptr %src, align 1
+ store <32 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i8, ptr %intermediate, i64 %byteOff
+ %chunk = load <32 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v32i8(<32 x i8> %chunk)
+ ret void
+}
+
+;; Special test
+
+define void @load-2byte-chunk-of-8byte-alloca-with-2byte-step(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-2byte-chunk-of-8byte-alloca-with-2byte-step(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [8 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <8 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <8 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i16, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load <2 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v2i8(<2 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [8 x i8], align 64
+ %init = load <8 x i8>, ptr %src, align 1
+ store <8 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i16, ptr %intermediate, i64 %byteOff
+ %chunk = load <2 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v2i8(<2 x i8> %chunk)
+ ret void
+}
+
+define void @load-volatile-2byte-chunk-of-8byte-alloca-with-2byte-step(ptr %src, i64 %byteOff) {
+; CHECK-ALL-LABEL: @load-volatile-2byte-chunk-of-8byte-alloca-with-2byte-step(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [8 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <8 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <8 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i16, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: [[CHUNK:%.*]] = load volatile <2 x i8>, ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: call void @use.v2i8(<2 x i8> [[CHUNK]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [8 x i8], align 64
+ %init = load <8 x i8>, ptr %src, align 1
+ store <8 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i16, ptr %intermediate, i64 %byteOff
+ %chunk = load volatile <2 x i8>, ptr %intermediate.off.addr, align 1
+ call void @use.v2i8(<2 x i8> %chunk)
+ ret void
+}
+
+define void @store-2byte-chunk-of-8byte-alloca-with-2byte-step(ptr %src, i64 %byteOff, <2 x i8> %reinit) {
+; CHECK-ALL-LABEL: @store-2byte-chunk-of-8byte-alloca-with-2byte-step(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [8 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <8 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <8 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i16, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: store <2 x i8> [[REINIT:%.*]], ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: [[FINAL:%.*]] = load <8 x i8>, ptr [[INTERMEDIATE]], align 1
+; CHECK-ALL-NEXT: call void @use.v8i8(<8 x i8> [[FINAL]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [8 x i8], align 64
+ %init = load <8 x i8>, ptr %src, align 1
+ store <8 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i16, ptr %intermediate, i64 %byteOff
+ store <2 x i8> %reinit, ptr %intermediate.off.addr, align 1
+ %final = load <8 x i8>, ptr %intermediate, align 1
+ call void @use.v8i8(<8 x i8> %final)
+ ret void
+}
+
+define void @store-volatile-2byte-chunk-of-8byte-alloca-with-2byte-step(ptr %src, i64 %byteOff, <2 x i8> %reinit) {
+; CHECK-ALL-LABEL: @store-volatile-2byte-chunk-of-8byte-alloca-with-2byte-step(
+; CHECK-ALL-NEXT: [[INTERMEDIATE:%.*]] = alloca [8 x i8], align 64
+; CHECK-ALL-NEXT: [[INIT:%.*]] = load <8 x i8>, ptr [[SRC:%.*]], align 1
+; CHECK-ALL-NEXT: store <8 x i8> [[INIT]], ptr [[INTERMEDIATE]], align 64
+; CHECK-ALL-NEXT: [[INTERMEDIATE_OFF_ADDR:%.*]] = getelementptr inbounds i16, ptr [[INTERMEDIATE]], i64 [[BYTEOFF:%.*]]
+; CHECK-ALL-NEXT: store volatile <2 x i8> [[REINIT:%.*]], ptr [[INTERMEDIATE_OFF_ADDR]], align 1
+; CHECK-ALL-NEXT: [[FINAL:%.*]] = load <8 x i8>, ptr [[INTERMEDIATE]], align 1
+; CHECK-ALL-NEXT: call void @use.v8i8(<8 x i8> [[FINAL]])
+; CHECK-ALL-NEXT: ret void
+;
+ %intermediate = alloca [8 x i8], align 64
+ %init = load <8 x i8>, ptr %src, align 1
+ store <8 x i8> %init, ptr %intermediate, align 64
+ %intermediate.off.addr = getelementptr inbounds i16, ptr %intermediate, i64 %byteOff
+ store volatile <2 x i8> %reinit, ptr %intermediate.off.addr, align 1
+ %final = load <8 x i8>, ptr %intermediate, align 1
+ call void @use.v8i8(<8 x i8> %final)
+ ret void
+}
+
+declare void @use.v1i8(<1 x i8>)
+declare void @use.v2i8(<2 x i8>)
+declare void @use.v4i8(<4 x i8>)
+declare void @use.v8i8(<8 x i8>)
+declare void @use.v16i8(<16 x i8>)
+declare void @use.v32i8(<32 x i8>)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-BE-32: {{.*}}
+; CHECK-BE-64: {{.*}}
+; CHECK-LE-32: {{.*}}
+; CHECK-LE-64: {{.*}}
+; CHECK-SCALAR: {{.*}}
+; CHECK-SCALAR-32: {{.*}}
+; CHECK-SCALAR-64: {{.*}}
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