[PATCH] D129735: [RISCV] Add new pass to transform undef to pseudo for vector values.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:201
+  VRegInfo *VRegInfos = new VRegInfo[NumVirtRegs];
+  Changed |= DDL.getSubRegisterLaneBitInfo(MF, VRegInfos);
+
----------------
Isn't this calculating for the entire function? But handleSubReg is called for individual instructions. So we'll be recomputing information right?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735