[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

[Sergei Barannikov via Phabricator via llvm-commits]

barannikov88 added inline comments.


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Comment at: llvm/lib/TargetParser/CMakeLists.txt:29
+# LLVMTargetParser. See https://stackoverflow.com/a/25681179
+target_include_directories(LLVMTargetParser PUBLIC $<BUILD_INTERFACE:${LLVM_LIBRARY_DIR}/TargetParser/>)
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Will it work if RISC-V target is not compiled-in?
This does not strictly add a cyclic dependency, but it would still be nice to avoid dependency on higher-level components.
Is it possible / reasonable to extract the part of the RISCV.td that relates to this component and put it separate td file in this directory? Or is it tightly coupled with the rest of the target description?



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Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:15
+#include "llvm/TableGen/Record.h"
+#include <iostream>
+namespace llvm {
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<iostream> [[ https://llvm.org/docs/CodingStandards.html#include-iostream-is-forbidden | is forbidden ]] by the coding standards.



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Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:16
+#include <iostream>
+namespace llvm {
+
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This [[ https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions | should be ]] `using namespace llvm;`


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Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:18
+
+std::string getEnumFeatures(Record &Rec) {
+  std::vector<Record *> Features = Rec.getValueAsListOfDefs("Features");
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This should be `static`.


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Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:20
+  std::vector<Record *> Features = Rec.getValueAsListOfDefs("Features");
+  if (std::find_if(Features.begin(), Features.end(), [](Record *R) {
+        return R->getName() == "Feature64Bit";
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(suggestion) LLVM's version of find_if accepts ranges, which is a bit shorter.


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Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:28
+
+void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
+  const auto &Map = RK.getDefs();
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This function does not seem to mutate RecordKeeper, so it should be `const`.


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Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:37
+  // Iterate on all definition records.
+  for (auto &Def : Map) {
+    const auto &Record = Def.second;
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Should also `const`, same for the loop below.


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Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:52
+  for (auto &Def : Map) {
+    const auto &Record = Def.second;
+    if (Record->isSubClassOf("RISCVProcessorModelTUNE_PROC"))
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Same for the loop above.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D137517/new/

https://reviews.llvm.org/D137517