[llvm] 69e75ae - CodeGen: Don't lazily construct MachineFunctionInfo
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 21 07:50:33 PST 2022
Author: Matt Arsenault
Date: 2022-12-21T10:49:32-05:00
New Revision: 69e75ae695d9ef1360a2a1fbefd6e0e0456c3f7b
URL: https://github.com/llvm/llvm-project/commit/69e75ae695d9ef1360a2a1fbefd6e0e0456c3f7b
DIFF: https://github.com/llvm/llvm-project/commit/69e75ae695d9ef1360a2a1fbefd6e0e0456c3f7b.diff
LOG: CodeGen: Don't lazily construct MachineFunctionInfo
This fixes what I consider to be an API flaw I've tripped over
multiple times. The point this is constructed isn't well defined, so
depending on where this is first called, you can conclude different
information based on the MachineFunction. For example, the AMDGPU
implementation inspected the MachineFrameInfo on construction for the
stack objects and if the frame has calls. This kind of worked in
SelectionDAG which visited all allocas up front, but broke in
GlobalISel which hasn't visited any of the IR when arguments are
lowered.
I've run into similar problems before with the MIR parser and trying
to make use of other MachineFunction fields, so I think it's best to
just categorically disallow dependency on the MachineFunction state in
the constructor and to always construct this at the same time as the
MachineFunction itself.
A missing feature I still could use is a way to access an custom
analysis pass on the IR here.
Added:
Modified:
llvm/include/llvm/CodeGen/MachineFunction.h
llvm/include/llvm/Target/TargetMachine.h
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/MachineModuleInfo.cpp
llvm/lib/CodeGen/ResetMachineFunctionPass.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.h
llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp
llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h
llvm/lib/Target/AMDGPU/R600TargetMachine.h
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
llvm/lib/Target/ARC/ARCTargetMachine.cpp
llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/lib/Target/ARM/ARMTargetMachine.h
llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
llvm/lib/Target/AVR/AVRTargetMachine.cpp
llvm/lib/Target/AVR/AVRTargetMachine.h
llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h
llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
llvm/lib/Target/Hexagon/HexagonTargetMachine.h
llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h
llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
llvm/lib/Target/Lanai/LanaiTargetMachine.h
llvm/lib/Target/LoongArch/LoongArchMachineFunctionInfo.h
llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h
llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
llvm/lib/Target/MSP430/MSP430TargetMachine.h
llvm/lib/Target/Mips/MipsMachineFunction.h
llvm/lib/Target/Mips/MipsTargetMachine.cpp
llvm/lib/Target/Mips/MipsTargetMachine.h
llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp
llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/lib/Target/PowerPC/PPCTargetMachine.h
llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.h
llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h
llvm/lib/Target/Sparc/SparcTargetMachine.cpp
llvm/lib/Target/Sparc/SparcTargetMachine.h
llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h
llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
llvm/lib/Target/SystemZ/SystemZTargetMachine.h
llvm/lib/Target/VE/VEMachineFunctionInfo.h
llvm/lib/Target/VE/VETargetMachine.cpp
llvm/lib/Target/VE/VETargetMachine.h
llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
llvm/lib/Target/X86/X86MachineFunctionInfo.h
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/lib/Target/X86/X86TargetMachine.h
llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h
llvm/lib/Target/XCore/XCoreTargetMachine.cpp
llvm/lib/Target/XCore/XCoreTargetMachine.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 4d2e5d38c5a6..3cb8d7b35e37 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -99,9 +99,10 @@ struct MachineFunctionInfo {
/// supplied allocator.
///
/// This function can be overridden in a derive class.
- template<typename Ty>
- static Ty *create(BumpPtrAllocator &Allocator, MachineFunction &MF) {
- return new (Allocator.Allocate<Ty>()) Ty(MF);
+ template <typename FuncInfoTy, typename SubtargetTy = TargetSubtargetInfo>
+ static FuncInfoTy *create(BumpPtrAllocator &Allocator, const Function &F,
+ const SubtargetTy *STI) {
+ return new (Allocator.Allocate<FuncInfoTy>()) FuncInfoTy(F, STI);
}
template <typename Ty>
@@ -753,14 +754,12 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
///
template<typename Ty>
Ty *getInfo() {
- if (!MFInfo)
- MFInfo = Ty::template create<Ty>(Allocator, *this);
return static_cast<Ty*>(MFInfo);
}
template<typename Ty>
const Ty *getInfo() const {
- return const_cast<MachineFunction*>(this)->getInfo<Ty>();
+ return static_cast<const Ty *>(MFInfo);
}
template <typename Ty> Ty *cloneInfo(const Ty &Old) {
@@ -769,6 +768,9 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
return static_cast<Ty *>(MFInfo);
}
+ /// Initialize the target specific MachineFunctionInfo
+ void initTargetMachineFunctionInfo(const TargetSubtargetInfo &STI);
+
MachineFunctionInfo *cloneInfoFrom(
const MachineFunction &OrigMF,
const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB) {
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index 57365d2c74d6..6361373ba71b 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -17,6 +17,7 @@
#include "llvm/ADT/Triple.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/PassManager.h"
+#include "llvm/Support/Allocator.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/PGOOptions.h"
@@ -63,6 +64,7 @@ class PassManagerBase;
}
using legacy::PassManagerBase;
+struct MachineFunctionInfo;
namespace yaml {
struct MachineFunctionInfo;
}
@@ -136,6 +138,13 @@ class TargetMachine {
return nullptr;
}
+ /// Create the target's instance of MachineFunctionInfo
+ virtual MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return nullptr;
+ }
+
/// Allocate and return a default initialized instance of the YAML
/// representation for the MachineFunctionInfo.
virtual yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const {
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index 78b49c923662..c6653ae3a665 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -187,6 +187,7 @@ void MachineFunction::init() {
RegInfo = nullptr;
MFInfo = nullptr;
+
// We can realign the stack if the target supports it and the user hasn't
// explicitly asked us not to.
bool CanRealignSP = STI->getFrameLowering()->isStackRealignable() &&
@@ -232,6 +233,12 @@ void MachineFunction::init() {
PSVManager = std::make_unique<PseudoSourceValueManager>(getTarget());
}
+void MachineFunction::initTargetMachineFunctionInfo(
+ const TargetSubtargetInfo &STI) {
+ assert(!MFInfo && "MachineFunctionInfo already set");
+ MFInfo = Target.createMachineFunctionInfo(Allocator, F, &STI);
+}
+
MachineFunction::~MachineFunction() {
clear();
}
diff --git a/llvm/lib/CodeGen/MachineModuleInfo.cpp b/llvm/lib/CodeGen/MachineModuleInfo.cpp
index 23d55a5df9f5..7a5a6c294ecf 100644
--- a/llvm/lib/CodeGen/MachineModuleInfo.cpp
+++ b/llvm/lib/CodeGen/MachineModuleInfo.cpp
@@ -118,6 +118,7 @@ MachineFunction &MachineModuleInfo::getOrCreateMachineFunction(Function &F) {
// No pre-existing machine function, create a new one.
const TargetSubtargetInfo &STI = *TM.getSubtargetImpl(F);
MF = new MachineFunction(F, TM, STI, NextFnNum++, *this);
+ MF->initTargetMachineFunctionInfo(STI);
// Update the set entry.
I.first->second.reset(MF);
} else {
diff --git a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp
index 0f73973c8a51..0ad6ef84220a 100644
--- a/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp
+++ b/llvm/lib/CodeGen/ResetMachineFunctionPass.cpp
@@ -66,6 +66,8 @@ namespace {
LLVM_DEBUG(dbgs() << "Resetting: " << MF.getName() << '\n');
++NumFunctionsReset;
MF.reset();
+ MF.initTargetMachineFunctionInfo(MF.getSubtarget());
+
if (EmitFallbackDiag) {
const Function &F = MF.getFunction();
DiagnosticInfoISelFallback DiagFallback(F);
diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
index 0f2c353e748b..961a19317d66 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
@@ -82,16 +82,14 @@ static bool ShouldSignWithBKey(const Function &F, const AArch64Subtarget &STI) {
return Key.equals_insensitive("b_key");
}
-AArch64FunctionInfo::AArch64FunctionInfo(MachineFunction &MF) {
- const Function &F = MF.getFunction();
- const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
-
+AArch64FunctionInfo::AArch64FunctionInfo(const Function &F,
+ const AArch64Subtarget *STI) {
// If we already know that the function doesn't have a redzone, set
// HasRedZone here.
if (F.hasFnAttribute(Attribute::NoRedZone))
HasRedZone = false;
std::tie(SignReturnAddress, SignReturnAddressAll) = GetSignReturnAddress(F);
- SignWithBKey = ShouldSignWithBKey(F, STI);
+ SignWithBKey = ShouldSignWithBKey(F, *STI);
// TODO: skip functions that have no instrumented allocas for optimization
IsMTETagged = F.hasFnAttribute(Attribute::SanitizeMemTag);
diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
index b3dbf04676f9..d82fb436925e 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
@@ -31,6 +31,7 @@ namespace yaml {
struct AArch64FunctionInfo;
} // end namespace yaml
+class AArch64Subtarget;
class MachineInstr;
/// AArch64FunctionInfo - This class is derived from MachineFunctionInfo and
@@ -192,7 +193,7 @@ class AArch64FunctionInfo final : public MachineFunctionInfo {
mutable std::optional<bool> NeedsAsyncDwarfUnwindInfo;
public:
- explicit AArch64FunctionInfo(MachineFunction &MF);
+ AArch64FunctionInfo(const Function &F, const AArch64Subtarget *STI);
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index b2844c4c6f93..037745c83ca7 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -841,6 +841,13 @@ void AArch64PassConfig::addPreEmitPass2() {
addPass(createUnpackMachineBundles(nullptr));
}
+MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return AArch64FunctionInfo::create<AArch64FunctionInfo>(
+ Allocator, F, static_cast<const AArch64Subtarget *>(STI));
+}
+
yaml::MachineFunctionInfo *
AArch64TargetMachine::createDefaultFuncInfoYAML() const {
return new yaml::AArch64FunctionInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index ae9d706be006..e9b5f4820b79 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -49,6 +49,10 @@ class AArch64TargetMachine : public LLVMTargetMachine {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
yaml::MachineFunctionInfo *
convertFuncInfoToYAML(const MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
index 9f2e2bfdaf78..a6a32b98f44c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
@@ -16,17 +16,15 @@
using namespace llvm;
-AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF)
- : IsEntryFunction(AMDGPU::isEntryFunctionCC(
- MF.getFunction().getCallingConv())),
+AMDGPUMachineFunction::AMDGPUMachineFunction(const Function &F,
+ const AMDGPUSubtarget &ST)
+ : IsEntryFunction(AMDGPU::isEntryFunctionCC(F.getCallingConv())),
IsModuleEntryFunction(
- AMDGPU::isModuleEntryFunctionCC(MF.getFunction().getCallingConv())),
- NoSignedZerosFPMath(MF.getTarget().Options.NoSignedZerosFPMath) {
- const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF);
+ AMDGPU::isModuleEntryFunctionCC(F.getCallingConv())),
+ NoSignedZerosFPMath(false) {
// FIXME: Should initialize KernArgSize based on ExplicitKernelArgOffset,
// except reserved size is not correctly aligned.
- const Function &F = MF.getFunction();
Attribute MemBoundAttr = F.getFnAttribute("amdgpu-memory-bound");
MemoryBound = MemBoundAttr.getValueAsBool();
@@ -46,6 +44,11 @@ AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF)
CallingConv::ID CC = F.getCallingConv();
if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL)
ExplicitKernArgSize = ST.getExplicitKernArgSize(F, MaxKernArgAlign);
+
+ // FIXME: Shouldn't be target specific
+ Attribute NSZAttr = F.getFnAttribute("no-signed-zeros-fp-math");
+ NoSignedZerosFPMath =
+ NSZAttr.isStringAttribute() && NSZAttr.getValueAsString() == "true";
}
unsigned AMDGPUMachineFunction::allocateLDSGlobal(const DataLayout &DL,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
index 8c5d7b0d10c2..f27f8252a4d8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
@@ -19,6 +19,9 @@
namespace llvm {
+class AMDGPUSubtarget;
+class GCNSubtarget;
+
class AMDGPUMachineFunction : public MachineFunctionInfo {
/// A map to keep track of local memory objects and their offsets within the
/// local memory space.
@@ -60,7 +63,7 @@ class AMDGPUMachineFunction : public MachineFunctionInfo {
bool WaveLimiter = false;
public:
- AMDGPUMachineFunction(const MachineFunction &MF);
+ AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST);
uint64_t getExplicitKernArgSize() const {
return ExplicitKernArgSize;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 7bda7eda6822..107fc249516e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -25,6 +25,7 @@
#include "GCNSchedStrategy.h"
#include "GCNVOPDUtils.h"
#include "R600.h"
+#include "R600MachineFunctionInfo.h"
#include "R600TargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
@@ -1087,6 +1088,13 @@ AMDGPUPassConfig::createMachineScheduler(MachineSchedContext *C) const {
return DAG;
}
+MachineFunctionInfo *R600TargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return R600MachineFunctionInfo::create<R600MachineFunctionInfo>(
+ Allocator, F, static_cast<const R600Subtarget *>(STI));
+}
+
//===----------------------------------------------------------------------===//
// GCN Pass Setup
//===----------------------------------------------------------------------===//
@@ -1403,6 +1411,13 @@ TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
return new GCNPassConfig(*this, PM);
}
+MachineFunctionInfo *GCNTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return SIMachineFunctionInfo::create<SIMachineFunctionInfo>(
+ Allocator, F, static_cast<const GCNSubtarget *>(STI));
+}
+
yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
return new yaml::SIMachineFunctionInfo();
}
@@ -1411,7 +1426,7 @@ yaml::MachineFunctionInfo *
GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
return new yaml::SIMachineFunctionInfo(
- *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
+ *MFI, *MF.getSubtarget<GCNSubtarget>().getRegisterInfo(), MF);
}
bool GCNTargetMachine::parseMachineFunctionInfo(
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index 3e95573415ca..ce93704b78f4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -92,6 +92,10 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
return true;
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
yaml::MachineFunctionInfo *
convertFuncInfoToYAML(const MachineFunction &MF) const override;
diff --git a/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp
index 65011a9eadf8..4254cd3c2008 100644
--- a/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp
@@ -8,8 +8,10 @@
//===----------------------------------------------------------------------===//
#include "R600MachineFunctionInfo.h"
+#include "R600Subtarget.h"
using namespace llvm;
-R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF)
- : AMDGPUMachineFunction(MF) { }
+R600MachineFunctionInfo::R600MachineFunctionInfo(const Function &F,
+ const R600Subtarget *STI)
+ : AMDGPUMachineFunction(F, *STI) {}
diff --git a/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h
index 6a5ac9023329..a8abf56f52ba 100644
--- a/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h
@@ -16,9 +16,11 @@
namespace llvm {
+class R600Subtarget;
+
class R600MachineFunctionInfo final : public AMDGPUMachineFunction {
public:
- R600MachineFunctionInfo(const MachineFunction &MF);
+ R600MachineFunctionInfo(const Function &F, const R600Subtarget *STI);
unsigned CFStackSize;
};
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.h b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
index ef5cc32bbbfd..f0e3cd352642 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
@@ -43,6 +43,10 @@ class R600TargetMachine final : public AMDGPUTargetMachine {
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
bool isMachineVerifierClean() const override { return false; }
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index 6eea030afb00..b2a433dd3db9 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -29,10 +29,16 @@
using namespace llvm;
-SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
- : AMDGPUMachineFunction(MF),
- Mode(MF.getFunction()),
- GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
+const GCNTargetMachine &getTM(const GCNSubtarget *STI) {
+ const SITargetLowering *TLI = STI->getTargetLowering();
+ return static_cast<const GCNTargetMachine &>(TLI->getTargetMachine());
+}
+
+SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
+ const GCNSubtarget *STI)
+ : AMDGPUMachineFunction(F, *STI),
+ Mode(F),
+ GWSResourcePSV(getTM(STI)),
PrivateSegmentBuffer(false),
DispatchPtr(false),
QueuePtr(false),
@@ -52,8 +58,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
ImplicitArgPtr(false),
GITPtrHigh(0xffffffff),
HighBitsOf32BitAddress(0) {
- const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
- const Function &F = MF.getFunction();
+ const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI);
FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
WavesPerEU = ST.getWavesPerEU(F);
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c0cfc36e0a96..3ad53b7cbcc3 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -533,8 +533,8 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const;
public:
- SIMachineFunctionInfo(const MachineFunction &MF);
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
+ SIMachineFunctionInfo(const Function &F, const GCNSubtarget *STI);
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h b/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
index 454206037498..cace92a2b8fb 100644
--- a/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
+++ b/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
@@ -27,11 +27,7 @@ class ARCFunctionInfo : public MachineFunctionInfo {
unsigned ReturnStackOffset;
public:
- ARCFunctionInfo()
- : ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
- ReturnStackOffset(-1U), MaxCallStackReq(0) {}
-
- explicit ARCFunctionInfo(MachineFunction &MF)
+ explicit ARCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
: ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
ReturnStackOffset(-1U), MaxCallStackReq(0) {}
~ARCFunctionInfo() {}
diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp
index b51e2246de32..ff41d3747475 100644
--- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp
+++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp
@@ -79,6 +79,12 @@ void ARCPassConfig::addPreRegAlloc() {
addPass(createARCOptAddrMode());
}
+MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return ARCFunctionInfo::create<ARCFunctionInfo>(Allocator, F, STI);
+}
+
// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {
RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget());
diff --git a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
index 9596e88deb18..aa9d8b54d963 100644
--- a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
@@ -13,12 +13,11 @@ using namespace llvm;
void ARMFunctionInfo::anchor() {}
-static bool GetBranchTargetEnforcement(MachineFunction &MF) {
- const auto &Subtarget = MF.getSubtarget<ARMSubtarget>();
- if (!Subtarget.isMClass() || !Subtarget.hasV7Ops())
+static bool GetBranchTargetEnforcement(const Function &F,
+ const ARMSubtarget *Subtarget) {
+ if (!Subtarget->isMClass() || !Subtarget->hasV7Ops())
return false;
- const Function &F = MF.getFunction();
if (!F.hasFnAttribute("branch-target-enforcement")) {
if (const auto *BTE = mdconst::extract_or_null<ConstantInt>(
F.getParent()->getModuleFlag("branch-target-enforcement")))
@@ -61,17 +60,14 @@ static std::pair<bool, bool> GetSignReturnAddress(const Function &F) {
return {true, false};
}
-ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF)
- : isThumb(MF.getSubtarget<ARMSubtarget>().isThumb()),
- hasThumb2(MF.getSubtarget<ARMSubtarget>().hasThumb2()),
- IsCmseNSEntry(MF.getFunction().hasFnAttribute("cmse_nonsecure_entry")),
- IsCmseNSCall(MF.getFunction().hasFnAttribute("cmse_nonsecure_call")),
- BranchTargetEnforcement(GetBranchTargetEnforcement(MF)) {
-
- const auto &Subtarget = MF.getSubtarget<ARMSubtarget>();
- if (Subtarget.isMClass() && Subtarget.hasV7Ops())
- std::tie(SignReturnAddress, SignReturnAddressAll) =
- GetSignReturnAddress(MF.getFunction());
+ARMFunctionInfo::ARMFunctionInfo(const Function &F,
+ const ARMSubtarget *Subtarget)
+ : isThumb(Subtarget->isThumb()), hasThumb2(Subtarget->hasThumb2()),
+ IsCmseNSEntry(F.hasFnAttribute("cmse_nonsecure_entry")),
+ IsCmseNSCall(F.hasFnAttribute("cmse_nonsecure_call")),
+ BranchTargetEnforcement(GetBranchTargetEnforcement(F, Subtarget)) {
+ if (Subtarget->isMClass() && Subtarget->hasV7Ops())
+ std::tie(SignReturnAddress, SignReturnAddressAll) = GetSignReturnAddress(F);
}
MachineFunctionInfo *
diff --git a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
index e906fea1a810..aba1afec3d48 100644
--- a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
+++ b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
@@ -22,6 +22,8 @@
namespace llvm {
+class ARMSubtarget;
+
/// ARMFunctionInfo - This class is derived from MachineFunctionInfo and
/// contains private ARM-specific information for each MachineFunction.
class ARMFunctionInfo : public MachineFunctionInfo {
@@ -157,7 +159,7 @@ class ARMFunctionInfo : public MachineFunctionInfo {
public:
ARMFunctionInfo() = default;
- explicit ARMFunctionInfo(MachineFunction &MF);
+ explicit ARMFunctionInfo(const Function &F, const ARMSubtarget *STI);
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 5f1b7a13c24d..3a9bd0ed58a9 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -11,6 +11,7 @@
#include "ARMTargetMachine.h"
#include "ARM.h"
+#include "ARMMachineFunctionInfo.h"
#include "ARMMacroFusion.h"
#include "ARMSubtarget.h"
#include "ARMTargetObjectFile.h"
@@ -264,6 +265,13 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
+MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return ARMFunctionInfo::create<ARMFunctionInfo>(
+ Allocator, F, static_cast<const ARMSubtarget *>(STI));
+}
+
const ARMSubtarget *
ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
Attribute CPUAttr = F.getFnAttribute("target-cpu");
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index fdd806053d09..fb04433ec522 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -74,6 +74,10 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
bool targetSchedulesPostRAScheduling() const override { return true; };
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
/// Returns true if a cast between SrcAS and DestAS is a noop.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
// Addrspacecasts are always noops.
diff --git a/llvm/lib/Target/AVR/AVRMachineFunctionInfo.h b/llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
index da4c48559d9e..45c367a4dcd4 100644
--- a/llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
+++ b/llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
@@ -45,20 +45,15 @@ class AVRMachineFunctionInfo : public MachineFunctionInfo {
int VarArgsFrameIndex;
public:
- AVRMachineFunctionInfo()
- : HasSpills(false), HasAllocas(false), HasStackArgs(false),
- IsInterruptHandler(false), IsSignalHandler(false),
- CalleeSavedFrameSize(0), VarArgsFrameIndex(0) {}
-
- explicit AVRMachineFunctionInfo(MachineFunction &MF)
+ AVRMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
: HasSpills(false), HasAllocas(false), HasStackArgs(false),
CalleeSavedFrameSize(0), VarArgsFrameIndex(0) {
- unsigned CallConv = MF.getFunction().getCallingConv();
+ CallingConv::ID CallConv = F.getCallingConv();
- this->IsInterruptHandler = CallConv == CallingConv::AVR_INTR ||
- MF.getFunction().hasFnAttribute("interrupt");
- this->IsSignalHandler = CallConv == CallingConv::AVR_SIGNAL ||
- MF.getFunction().hasFnAttribute("signal");
+ this->IsInterruptHandler =
+ CallConv == CallingConv::AVR_INTR || F.hasFnAttribute("interrupt");
+ this->IsSignalHandler =
+ CallConv == CallingConv::AVR_SIGNAL || F.hasFnAttribute("signal");
}
MachineFunctionInfo *
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
index 6b159623db45..06a2c7d3ac1a 100644
--- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp
@@ -19,6 +19,7 @@
#include "llvm/MC/TargetRegistry.h"
#include "AVR.h"
+#include "AVRMachineFunctionInfo.h"
#include "AVRTargetObjectFile.h"
#include "MCTargetDesc/AVRMCTargetDesc.h"
#include "TargetInfo/AVRTargetInfo.h"
@@ -105,6 +106,13 @@ const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
return &SubTarget;
}
+MachineFunctionInfo *AVRTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return AVRMachineFunctionInfo::create<AVRMachineFunctionInfo>(Allocator, F,
+ STI);
+}
+
//===----------------------------------------------------------------------===//
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.h b/llvm/lib/Target/AVR/AVRTargetMachine.h
index 5ba689d3b849..ea29c8ecb479 100644
--- a/llvm/lib/Target/AVR/AVRTargetMachine.h
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.h
@@ -44,6 +44,10 @@ class AVRTargetMachine : public LLVMTargetMachine {
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
private:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
AVRSubtarget SubTarget;
diff --git a/llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h b/llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h
index 57e0d62481ad..51eda696709d 100644
--- a/llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h
+++ b/llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h
@@ -31,7 +31,7 @@ class CSKYMachineFunctionInfo : public MachineFunctionInfo {
unsigned PICLabelUId = 0;
public:
- CSKYMachineFunctionInfo(MachineFunction &) {}
+ CSKYMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
index e0cd0d2b1353..cb4a7a8c393f 100644
--- a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
@@ -40,7 +40,9 @@ class HexagonMachineFunctionInfo : public MachineFunctionInfo {
public:
HexagonMachineFunctionInfo() = default;
- HexagonMachineFunctionInfo(MachineFunction &MF) {}
+ HexagonMachineFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI) {}
+
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 15ade4c6b46d..aed075d54ee8 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -14,6 +14,7 @@
#include "Hexagon.h"
#include "HexagonISelLowering.h"
#include "HexagonLoopIdiomRecognition.h"
+#include "HexagonMachineFunctionInfo.h"
#include "HexagonMachineScheduler.h"
#include "HexagonTargetObjectFile.h"
#include "HexagonTargetTransformInfo.h"
@@ -289,6 +290,13 @@ HexagonTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(HexagonTTIImpl(this, F));
}
+MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
+ Allocator, F, STI);
+}
+
HexagonTargetMachine::~HexagonTargetMachine() = default;
namespace {
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 07213cfd7526..1818697476dd 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -45,6 +45,10 @@ class HexagonTargetMachine : public LLVMTargetMachine {
HexagonTargetObjectFile *getObjFileLowering() const override {
return static_cast<HexagonTargetObjectFile*>(TLOF.get());
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h b/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h
index edf5f2ee087e..81f4a122d022 100644
--- a/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h
@@ -38,7 +38,7 @@ class LanaiMachineFunctionInfo : public MachineFunctionInfo {
int VarArgsFrameIndex;
public:
- explicit LanaiMachineFunctionInfo(MachineFunction &MF)
+ LanaiMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
: VarArgsFrameIndex(0) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
index 5e427459a8d2..d9e958b0a2c7 100644
--- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
+++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
@@ -13,6 +13,7 @@
#include "LanaiTargetMachine.h"
#include "Lanai.h"
+#include "LanaiMachineFunctionInfo.h"
#include "LanaiTargetObjectFile.h"
#include "LanaiTargetTransformInfo.h"
#include "TargetInfo/LanaiTargetInfo.h"
@@ -72,6 +73,13 @@ LanaiTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(LanaiTTIImpl(this, F));
}
+MachineFunctionInfo *LanaiTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return LanaiMachineFunctionInfo::create<LanaiMachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
namespace {
// Lanai Code Generator Pass Configuration Options.
class LanaiPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.h b/llvm/lib/Target/Lanai/LanaiTargetMachine.h
index 35ffca7c833f..85e3b3f261fe 100644
--- a/llvm/lib/Target/Lanai/LanaiTargetMachine.h
+++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.h
@@ -48,6 +48,10 @@ class LanaiTargetMachine : public LLVMTargetMachine {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool isMachineVerifierClean() const override {
return false;
}
diff --git a/llvm/lib/Target/LoongArch/LoongArchMachineFunctionInfo.h b/llvm/lib/Target/LoongArch/LoongArchMachineFunctionInfo.h
index 47b021e2f78f..0d819154a89c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchMachineFunctionInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchMachineFunctionInfo.h
@@ -37,7 +37,8 @@ class LoongArchMachineFunctionInfo : public MachineFunctionInfo {
int BranchRelaxationSpillFrameIndex = -1;
public:
- LoongArchMachineFunctionInfo(const MachineFunction &MF) {}
+ LoongArchMachineFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h b/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h
index 93b388255877..74ffaebe429f 100644
--- a/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h
+++ b/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h
@@ -40,8 +40,8 @@ class MSP430MachineFunctionInfo : public MachineFunctionInfo {
public:
MSP430MachineFunctionInfo() = default;
- explicit MSP430MachineFunctionInfo(MachineFunction &MF)
- : CalleeSavedFrameSize(0), ReturnAddrIndex(0), SRetReturnReg(0) {}
+ MSP430MachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
+ : CalleeSavedFrameSize(0), ReturnAddrIndex(0), SRetReturnReg(0) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
index f5a4fbf54f45..e89b89f65a46 100644
--- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
+++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
@@ -12,6 +12,7 @@
#include "MSP430TargetMachine.h"
#include "MSP430.h"
+#include "MSP430MachineFunctionInfo.h"
#include "TargetInfo/MSP430TargetInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
@@ -72,6 +73,13 @@ TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
return new MSP430PassConfig(*this, PM);
}
+MachineFunctionInfo *MSP430TargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return MSP430MachineFunctionInfo::create<MSP430MachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
bool MSP430PassConfig::addInstSelector() {
// Install an instruction selector.
addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.h b/llvm/lib/Target/MSP430/MSP430TargetMachine.h
index 400a938f6990..30e1f7f4a80d 100644
--- a/llvm/lib/Target/MSP430/MSP430TargetMachine.h
+++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.h
@@ -43,6 +43,10 @@ class MSP430TargetMachine : public LLVMTargetMachine {
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
}; // MSP430TargetMachine.
} // end namespace llvm
diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.h b/llvm/lib/Target/Mips/MipsMachineFunction.h
index 7b17fd3ed0cd..b7b748838569 100644
--- a/llvm/lib/Target/Mips/MipsMachineFunction.h
+++ b/llvm/lib/Target/Mips/MipsMachineFunction.h
@@ -24,7 +24,7 @@ namespace llvm {
/// Mips target-specific information for each MachineFunction.
class MipsFunctionInfo : public MachineFunctionInfo {
public:
- MipsFunctionInfo(MachineFunction &MF) {}
+ MipsFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
index 58b8a72cb664..e5e8333ccf5d 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -15,6 +15,7 @@
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "Mips.h"
#include "Mips16ISelDAGToDAG.h"
+#include "MipsMachineFunction.h"
#include "MipsSEISelDAGToDAG.h"
#include "MipsSubtarget.h"
#include "MipsTargetObjectFile.h"
@@ -292,6 +293,12 @@ MipsTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(MipsTTIImpl(this, F));
}
+MachineFunctionInfo *MipsTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return MipsFunctionInfo::create<MipsFunctionInfo>(Allocator, F, STI);
+}
+
// Implemented by targets that want to run passes immediately before
// machine code is emitted.
void MipsPassConfig::addPreEmitPass() {
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index c4abb4bfefc3..d07e5bb2dfbc 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -64,6 +64,10 @@ class MipsTargetMachine : public LLVMTargetMachine {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
/// Returns true if a cast between SrcAS and DestAS is a noop.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
// Mips doesn't have any special address spaces so we just reserve
diff --git a/llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h b/llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
index 0a7b9cf468a6..77426f7f6da7 100644
--- a/llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
@@ -24,7 +24,7 @@ class NVPTXMachineFunctionInfo : public MachineFunctionInfo {
SmallVector<std::string, 8> ImageHandleList;
public:
- NVPTXMachineFunctionInfo(MachineFunction &MF) {}
+ NVPTXMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index 259ecbfacb21..dc207b01f57f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -15,6 +15,7 @@
#include "NVPTXAllocaHoisting.h"
#include "NVPTXAtomicLower.h"
#include "NVPTXLowerAggrCopies.h"
+#include "NVPTXMachineFunctionInfo.h"
#include "NVPTXTargetObjectFile.h"
#include "NVPTXTargetTransformInfo.h"
#include "TargetInfo/NVPTXTargetInfo.h"
@@ -201,6 +202,13 @@ TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
return new NVPTXPassConfig(*this, PM);
}
+MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
PB.registerPipelineParsingCallback(
[](StringRef PassName, FunctionPassManager &PM,
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
index 2b6ce69204f4..12005e0ebf39 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
@@ -63,6 +63,10 @@ class NVPTXTargetMachine : public LLVMTargetMachine {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
void registerPassBuilderCallbacks(PassBuilder &PB) override;
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp
index 9d6dfd16ff9d..b2089521c467 100644
--- a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp
@@ -20,7 +20,8 @@ static cl::opt<bool> PPCDisableNonVolatileCR(
cl::init(false), cl::Hidden);
void PPCFunctionInfo::anchor() {}
-PPCFunctionInfo::PPCFunctionInfo(const MachineFunction &MF)
+PPCFunctionInfo::PPCFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI)
: DisableNonVolatileCR(PPCDisableNonVolatileCR) {}
MachineFunctionInfo *
diff --git a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
index b918e723de00..df655a3be951 100644
--- a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
@@ -151,7 +151,7 @@ class PPCFunctionInfo : public MachineFunctionInfo {
std::vector<std::pair<Register, ISD::ArgFlagsTy>> LiveInAttrs;
public:
- explicit PPCFunctionInfo(const MachineFunction &MF);
+ explicit PPCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI);
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 4edbcb03cf17..3f51018bbed5 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -13,6 +13,7 @@
#include "PPCTargetMachine.h"
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "PPC.h"
+#include "PPCMachineFunctionInfo.h"
#include "PPCMachineScheduler.h"
#include "PPCMacroFusion.h"
#include "PPCSubtarget.h"
@@ -579,6 +580,12 @@ bool PPCTargetMachine::isLittleEndian() const {
return Endianness == Endian::LITTLE;
}
+MachineFunctionInfo *PPCTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return PPCFunctionInfo::create<PPCFunctionInfo>(Allocator, F, STI);
+}
+
static MachineSchedRegistry
PPCPreRASchedRegistry("ppc-prera",
"Run PowerPC PreRA specific scheduler",
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 9351d100af5f..5d4571b7323a 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -58,6 +58,11 @@ class PPCTargetMachine final : public LLVMTargetMachine {
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
bool isPPC64() const {
const Triple &TT = getTargetTriple();
diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
index b04b042d1c0f..2744072568ee 100644
--- a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
@@ -72,7 +72,7 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo {
SmallVector<Register, 8> SExt32Registers;
public:
- RISCVMachineFunctionInfo(const MachineFunction &MF) {}
+ RISCVMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index fa13c6a48499..e84318c10e9e 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -184,6 +184,13 @@ RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
return I.get();
}
+MachineFunctionInfo *RISCVTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
TargetTransformInfo
RISCVTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(RISCVTTIImpl(this, F));
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index d3102f122cb7..9d3e6e98954d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -44,6 +44,10 @@ class RISCVTargetMachine : public LLVMTargetMachine {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override;
diff --git a/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h b/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h
index e1a1568d28a2..f73cd6d1b131 100644
--- a/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h
+++ b/llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h
@@ -34,9 +34,9 @@ namespace llvm {
SparcMachineFunctionInfo()
: GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
IsLeafProc(false) {}
- explicit SparcMachineFunctionInfo(MachineFunction &MF)
- : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
- IsLeafProc(false) {}
+ SparcMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
+ : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
+ IsLeafProc(false) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 2912f9674002..30570e8c6a66 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -12,6 +12,7 @@
#include "SparcTargetMachine.h"
#include "LeonPasses.h"
#include "Sparc.h"
+#include "SparcMachineFunctionInfo.h"
#include "SparcTargetObjectFile.h"
#include "TargetInfo/SparcTargetInfo.h"
#include "llvm/CodeGen/Passes.h"
@@ -138,6 +139,13 @@ SparcTargetMachine::getSubtargetImpl(const Function &F) const {
return I.get();
}
+MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return SparcMachineFunctionInfo::create<SparcMachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
namespace {
/// Sparc Code Generator Pass Configuration Options.
class SparcPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index ee2d3ad00621..6e3c8e7df43f 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -42,6 +42,10 @@ class SparcTargetMachine : public LLVMTargetMachine {
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
};
/// Sparc 32-bit target machine
diff --git a/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h b/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h
index de73a5d86422..333195989a11 100644
--- a/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h
@@ -37,9 +37,9 @@ class SystemZMachineFunctionInfo : public MachineFunctionInfo {
unsigned NumLocalDynamics;
public:
- explicit SystemZMachineFunctionInfo(MachineFunction &MF)
- : VarArgsFirstGPR(0), VarArgsFirstFPR(0), VarArgsFrameIndex(0),
- RegSaveFrameIndex(0), FramePointerSaveIndex(0), NumLocalDynamics(0) {}
+ SystemZMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
+ : VarArgsFirstGPR(0), VarArgsFirstFPR(0), VarArgsFrameIndex(0),
+ RegSaveFrameIndex(0), FramePointerSaveIndex(0), NumLocalDynamics(0) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 87963c42b803..d5f8659b6046 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -9,6 +9,7 @@
#include "SystemZTargetMachine.h"
#include "MCTargetDesc/SystemZMCTargetDesc.h"
#include "SystemZ.h"
+#include "SystemZMachineFunctionInfo.h"
#include "SystemZMachineScheduler.h"
#include "SystemZTargetTransformInfo.h"
#include "TargetInfo/SystemZTargetInfo.h"
@@ -310,3 +311,10 @@ TargetTransformInfo
SystemZTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(SystemZTTIImpl(this, F));
}
+
+MachineFunctionInfo *SystemZTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return SystemZMachineFunctionInfo::create<SystemZMachineFunctionInfo>(
+ Allocator, F, STI);
+}
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
index d7e21cbe22fa..20d68fff170a 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -51,6 +51,10 @@ class SystemZTargetMachine : public LLVMTargetMachine {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool targetSchedulesPostRAScheduling() const override { return true; };
};
diff --git a/llvm/lib/Target/VE/VEMachineFunctionInfo.h b/llvm/lib/Target/VE/VEMachineFunctionInfo.h
index d9d30ad5b8c5..5c02315d5175 100644
--- a/llvm/lib/Target/VE/VEMachineFunctionInfo.h
+++ b/llvm/lib/Target/VE/VEMachineFunctionInfo.h
@@ -30,7 +30,7 @@ class VEMachineFunctionInfo : public MachineFunctionInfo {
public:
VEMachineFunctionInfo() : VarArgsFrameOffset(0), IsLeafProc(false) {}
- explicit VEMachineFunctionInfo(MachineFunction &MF)
+ VEMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
: VarArgsFrameOffset(0), IsLeafProc(false) {}
MachineFunctionInfo *
diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp
index 48337a6f8670..09421c3670d3 100644
--- a/llvm/lib/Target/VE/VETargetMachine.cpp
+++ b/llvm/lib/Target/VE/VETargetMachine.cpp
@@ -12,6 +12,7 @@
#include "VETargetMachine.h"
#include "TargetInfo/VETargetInfo.h"
#include "VE.h"
+#include "VEMachineFunctionInfo.h"
#include "VETargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
@@ -98,6 +99,13 @@ VETargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(VETTIImpl(this, F));
}
+MachineFunctionInfo *VETargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return VEMachineFunctionInfo::create<VEMachineFunctionInfo>(Allocator, F,
+ STI);
+}
+
namespace {
/// VE Code Generator Pass Configuration Options.
class VEPassConfig : public TargetPassConfig {
diff --git a/llvm/lib/Target/VE/VETargetMachine.h b/llvm/lib/Target/VE/VETargetMachine.h
index bb27322b5512..057ff16b7592 100644
--- a/llvm/lib/Target/VE/VETargetMachine.h
+++ b/llvm/lib/Target/VE/VETargetMachine.h
@@ -49,6 +49,10 @@ class VETargetMachine : public LLVMTargetMachine {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool isMachineVerifierClean() const override { return false; }
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
index 00bacbf4e85b..7622164449a5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
@@ -65,7 +65,8 @@ class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
bool CFGStackified = false;
public:
- explicit WebAssemblyFunctionInfo(MachineFunction &) {}
+ explicit WebAssemblyFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI) {}
~WebAssemblyFunctionInfo() override;
MachineFunctionInfo *
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index 60b91857ca2e..bced56f3a5b8 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -340,6 +340,13 @@ class WebAssemblyPassConfig final : public TargetPassConfig {
};
} // end anonymous namespace
+MachineFunctionInfo *WebAssemblyTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return WebAssemblyFunctionInfo::create<WebAssemblyFunctionInfo>(Allocator, F,
+ STI);
+}
+
TargetTransformInfo
WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
index a8c39bc986b0..04bf2de81fe6 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
@@ -47,6 +47,10 @@ class WebAssemblyTargetMachine final : public LLVMTargetMachine {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
bool usesPhysRegsForValues() const override { return false; }
diff --git a/llvm/lib/Target/X86/X86MachineFunctionInfo.h b/llvm/lib/Target/X86/X86MachineFunctionInfo.h
index 9b09f0c53f62..6d7cf165699b 100644
--- a/llvm/lib/Target/X86/X86MachineFunctionInfo.h
+++ b/llvm/lib/Target/X86/X86MachineFunctionInfo.h
@@ -132,9 +132,9 @@ class X86MachineFunctionInfo : public MachineFunctionInfo {
public:
X86MachineFunctionInfo() = default;
+ X86MachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
- explicit X86MachineFunctionInfo(MachineFunction &MF) {}
- explicit X86MachineFunctionInfo(const X86MachineFunctionInfo &) = default;
+ X86MachineFunctionInfo(const X86MachineFunctionInfo &) = default;
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index ab99bc2c1b8d..3e8e8af7c2cc 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -16,6 +16,7 @@
#include "X86.h"
#include "X86CallLowering.h"
#include "X86LegalizerInfo.h"
+#include "X86MachineFunctionInfo.h"
#include "X86MacroFusion.h"
#include "X86Subtarget.h"
#include "X86TargetObjectFile.h"
@@ -426,6 +427,13 @@ TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
return new X86PassConfig(*this, PM);
}
+MachineFunctionInfo *X86TargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return X86MachineFunctionInfo::create<X86MachineFunctionInfo>(Allocator, F,
+ STI);
+}
+
void X86PassConfig::addIRPasses() {
addPass(createAtomicExpandPass());
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index 1eca730d99e9..5ea51e2fc22c 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -54,6 +54,10 @@ class X86TargetMachine final : public LLVMTargetMachine {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool isJIT() const { return IsJIT; }
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
diff --git a/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h b/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h
index 6cdb1239750a..a89b4f786eb6 100644
--- a/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h
+++ b/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h
@@ -43,7 +43,8 @@ class XCoreFunctionInfo : public MachineFunctionInfo {
public:
XCoreFunctionInfo() = default;
- explicit XCoreFunctionInfo(MachineFunction &MF) {}
+ explicit XCoreFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
index 1e3fcf63a107..fe9490aeee37 100644
--- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -13,6 +13,7 @@
#include "MCTargetDesc/XCoreMCTargetDesc.h"
#include "TargetInfo/XCoreTargetInfo.h"
#include "XCore.h"
+#include "XCoreMachineFunctionInfo.h"
#include "XCoreTargetObjectFile.h"
#include "XCoreTargetTransformInfo.h"
#include "llvm/ADT/STLExtras.h"
@@ -111,3 +112,9 @@ TargetTransformInfo
XCoreTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(XCoreTTIImpl(this, F));
}
+
+MachineFunctionInfo *XCoreTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return XCoreFunctionInfo::create<XCoreFunctionInfo>(Allocator, F, STI);
+}
diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.h b/llvm/lib/Target/XCore/XCoreTargetMachine.h
index a5691b541291..b45287da3a1c 100644
--- a/llvm/lib/Target/XCore/XCoreTargetMachine.h
+++ b/llvm/lib/Target/XCore/XCoreTargetMachine.h
@@ -48,6 +48,10 @@ class XCoreTargetMachine : public LLVMTargetMachine {
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
};
} // end namespace llvm
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