[llvm] eb7b8e3 - [AAch64] Optimize muls with operands having enough zero bits.

[via llvm-commits]

Author: bipmis
Date: 2022-12-21T11:14:45Z
New Revision: eb7b8e3e2aab6bca3d4403ceb1402e10c4e853b6

URL: https://github.com/llvm/llvm-project/commit/eb7b8e3e2aab6bca3d4403ceb1402e10c4e853b6
DIFF: https://github.com/llvm/llvm-project/commit/eb7b8e3e2aab6bca3d4403ceb1402e10c4e853b6.diff

LOG: [AAch64] Optimize muls with operands having enough zero bits.

Fix the regression in the reported test case lagarith-preproc.c.
Specfic to the incorrect umsubl generation.

Differential Revision: https://reviews.llvm.org/D139411

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrInfo.td
    llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 01f21e38e8395..d82d794591157 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1972,7 +1972,7 @@ def : Pat<(i64 (ineg (mul top32Zero:$Rn, (zext GPR32:$Rm)))),
 
 def : Pat<(i64 (sub GPR64:$Ra, (mul top32Zero:$Rn, top32Zero:$Rm))),
           (UMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), GPR64:$Ra)>;
-def : Pat<(i64 (sub GPR64:$Ra, (mul GPR64:$Rn, (zext GPR32:$Rm)))),
+def : Pat<(i64 (sub GPR64:$Ra, (mul top32Zero:$Rn, (zext GPR32:$Rm)))),
           (UMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, GPR64:$Ra)>;
 } // AddedComplexity = 5
 

diff  --git a/llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll b/llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
index 44d31d9b44244..e9baefc750987 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
@@ -1384,3 +1384,18 @@ entry:
   %mul = mul i64 %and, %zext4
   ret i64 %mul
 }
+
+define i64 @regression_umsubl(i64 %a, i32 %b, i64 %c) {
+; CHECK-LABEL: regression_umsubl:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov w8, w1
+; CHECK-NEXT:    udiv x9, x0, x8
+; CHECK-NEXT:    msub x0, x9, x8, x2
+; CHECK-NEXT:    ret
+entry:
+  %zext1 = zext i32 %b to i64
+  %res = udiv i64 %a, %zext1
+  %mul = mul i64 %res, %zext1
+  %sub = sub i64 %c, %mul
+  ret i64 %sub
+}