[PATCH] D140465: [RISCV] Add DAG combine to fold (select C, (add X, Y), Y) -> (add (select C, X, 0), Y).

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Similar for sub, or, and xor. All ops that have 0 as a neutral value.
This is based on a similar tranform in InstCombine.

This allows us to remove some XVentanaCondOps patterns and
some code from DAGCombine for RISCVISD::SELECT_CC.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140465

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
  llvm/test/CodeGen/RISCV/select.ll
  llvm/test/CodeGen/RISCV/sextw-removal.ll

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