[PATCH] D140460: [RISCV][MC] Add support for experimental zfa extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:347
+  // We expect an 5-bit binary encoding of a floating-point constant here.
+  static unsigned int Exp_arr[31] = {
+      0b00000001, 0b01101111, 0b01110000, 0b01110111, 0b01111000, 0b01111011,
----------------
Can we use a smaller size than `unsigned int`?


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:355
+
+  static unsigned int Man_arr[31] = {
+      0b000, 0b000, 0b000, 0b000, 0b000, 0b000, 0b000, 0b000,
----------------
Same here


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td:88
+
+defm FMINM_S   : FPALU_rr_m<0b0010100, 0b010, "fminm.s", FINX, /*Commutable*/1>;
+defm FMAXM_S   : FPALU_rr_m<0b0010100, 0b011, "fmaxm.s", FINX, /*Commutable*/1>;
----------------
These instructions need a Zfa assembler predicate


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td:91
+
+defm FMINM_D   : FPALU_rr_m<0b0010101, 0b010, "fminm.d", DINX, /*Commutable*/1>;
+defm FMAXM_D   : FPALU_rr_m<0b0010101, 0b011, "fmaxm.d", DINX, /*Commutable*/1>;
----------------
These instructions need a Zfa and D assembler predicate


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td:94
+
+defm FMINM_H   : FPALU_rr_m<0b0010110, 0b010, "fminm.h", HINX, /*Commutable*/1>;
+defm FMAXM_H   : FPALU_rr_m<0b0010110, 0b011, "fmaxm.h", HINX, /*Commutable*/1>;
----------------
These instructions need a Zfa and Zfh assembler predicate


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140460/new/

https://reviews.llvm.org/D140460