[llvm] b6b30cb - [RISCV] Simplify some code in SELECT_CC combine. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-12-20T21:31:23-08:00
New Revision: b6b30cb291ffd6276c1e95d766b7ddfd2fc91493

URL: https://github.com/llvm/llvm-project/commit/b6b30cb291ffd6276c1e95d766b7ddfd2fc91493
DIFF: https://github.com/llvm/llvm-project/commit/b6b30cb291ffd6276c1e95d766b7ddfd2fc91493.diff

LOG: [RISCV] Simplify some code in SELECT_CC combine. NFC

An integer SELECT_CC should have all XLenVT operands, we don't
need to handle other cases.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 318278c9fd87..a5f2092ab215 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9846,19 +9846,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
       };
 
       if (isOrXorPattern()) {
-        SDValue Neg;
-        unsigned CmpSz = LHS.getSimpleValueType().getSizeInBits();
-        // We need mask of all zeros or ones with same size of the other
-        // operands.
-        if (CmpSz > VT.getSizeInBits())
-          Neg = DAG.getNode(ISD::TRUNCATE, DL, VT, LHS);
-        else if (CmpSz < VT.getSizeInBits())
-          Neg = DAG.getNode(ISD::AND, DL, VT,
-                            DAG.getNode(ISD::ANY_EXTEND, DL, VT, LHS),
-                            DAG.getConstant(1, DL, VT));
-        else
-          Neg = LHS;
-        SDValue Mask = DAG.getNegative(Neg, DL, VT);               // -x
+        assert(LHS.getValueType() == VT && "Unexpected VT!");
+        SDValue Mask = DAG.getNegative(LHS, DL, VT);             // -x
         SDValue And = DAG.getNode(ISD::AND, DL, VT, Mask, Src1); // Mask & z
         return DAG.getNode(Opcode, DL, VT, And, Src2);           // And Op y
       }