[PATCH] D140283: [RISCV] Move -riscv-v-vector-bits-max/min options to RISCVTargetMachine.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG011cbb3912c7: [RISCV] Move -riscv-v-vector-bits-max/min options to RISCVTargetMachine. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D140283?vs=483869&id=484349#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140283/new/

https://reviews.llvm.org/D140283

Files:
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

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