[PATCH] D140421: [RISCV] Add more XVentanCondOps patterns.

[Craig Topper via Phabricator via llvm-commits]

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Add patterns with seteq/setne conditions.

We don't have instructions for seteq/setne except for comparing
with zero and need to emit an ADDI or XOR before a seqz/snez to
compare other values.

The select ISD node takes a 0/1 value for the condition, but the
VT_MASKC(N) instructions check all XLen bits for zero or non-zero.
We can use this to avoid the seqz/snez in many cases.

This is pretty ridiculous number of patterns. I wonder if we could
use some ComplexPatterns to merge them, but I'd like to do that as
a follow up and focus on correctness of the result in this patch.

I also wonder if we really need the binop patterns. They are
non-canonical according to InstCombine. If we do need them, it is
probably better to implement the same InstCombine transform in
DAGCombine instead.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140421

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
  llvm/test/CodeGen/RISCV/select.ll
  llvm/test/CodeGen/RISCV/xventanacondops.ll

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