[llvm] 48a3629 - [RISCV] Use default attributes for intrinsics
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 20 08:36:19 PST 2022
Author: Craig Topper
Date: 2022-12-20T08:21:07-08:00
New Revision: 48a362929916b7460b5634de264d490a5ad82f03
URL: https://github.com/llvm/llvm-project/commit/48a362929916b7460b5634de264d490a5ad82f03
DIFF: https://github.com/llvm/llvm-project/commit/48a362929916b7460b5634de264d490a5ad82f03.diff
LOG: [RISCV] Use default attributes for intrinsics
This switches a large subset of RISC-V intrinsics to use default
attributes (nosync, nofree, nocallback and willreturn).
I didn't reformat a lot of this. I can spend more time on that if
we think it's important.
Reviewed By: nikic, asb, eopXD
Differential Revision: https://reviews.llvm.org/D140360
Added:
Modified:
llvm/include/llvm/IR/IntrinsicsRISCV.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 002920a2e194..26fb0d64b402 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -80,13 +80,13 @@ let TargetPrefix = "riscv" in {
let TargetPrefix = "riscv" in {
class BitManipGPRIntrinsics
- : Intrinsic<[llvm_any_ty],
- [LLVMMatchType<0>],
- [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+ : DefaultAttrsIntrinsic<[llvm_any_ty],
+ [LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable]>;
class BitManipGPRGPRIntrinsics
- : Intrinsic<[llvm_any_ty],
- [LLVMMatchType<0>, LLVMMatchType<0>],
- [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+ : DefaultAttrsIntrinsic<[llvm_any_ty],
+ [LLVMMatchType<0>, LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable]>;
// Zbb
def int_riscv_orc_b : BitManipGPRIntrinsics;
@@ -161,7 +161,7 @@ let TargetPrefix = "riscv" in {
// For unit stride mask load
// Input: (pointer, vl)
class RISCVUSMLoad
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMPointerType<LLVMMatchType<0>>,
llvm_anyint_ty],
[NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic {
@@ -170,7 +170,7 @@ let TargetPrefix = "riscv" in {
// For unit stride load
// Input: (passthru, pointer, vl)
class RISCVUSLoad
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>,
llvm_anyint_ty],
@@ -183,7 +183,7 @@ let TargetPrefix = "riscv" in {
// NOTE: We model this with default memory properties since we model writing
// VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
class RISCVUSLoadFF
- : Intrinsic<[llvm_anyvector_ty, llvm_anyint_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty, llvm_anyint_ty],
[LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>, LLVMMatchType<1>],
[NoCapture<ArgIndex<1>>]>,
@@ -193,7 +193,7 @@ let TargetPrefix = "riscv" in {
// For unit stride load with mask
// Input: (maskedoff, pointer, mask, vl, policy)
class RISCVUSLoadMasked
- : Intrinsic<[llvm_anyvector_ty ],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty ],
[LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
@@ -208,7 +208,7 @@ let TargetPrefix = "riscv" in {
// NOTE: We model this with default memory properties since we model writing
// VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
class RISCVUSLoadFFMasked
- : Intrinsic<[llvm_anyvector_ty, llvm_anyint_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty, llvm_anyint_ty],
[LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
@@ -219,7 +219,7 @@ let TargetPrefix = "riscv" in {
// For strided load with passthru operand
// Input: (passthru, pointer, stride, vl)
class RISCVSLoad
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>,
llvm_anyint_ty, LLVMMatchType<1>],
@@ -229,7 +229,7 @@ let TargetPrefix = "riscv" in {
// For strided load with mask
// Input: (maskedoff, pointer, stride, mask, vl, policy)
class RISCVSLoadMasked
- : Intrinsic<[llvm_anyvector_ty ],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty ],
[LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>,
@@ -241,7 +241,7 @@ let TargetPrefix = "riscv" in {
// For indexed load with passthru operand
// Input: (passthru, pointer, index, vl)
class RISCVILoad
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>,
llvm_anyvector_ty, llvm_anyint_ty],
@@ -251,7 +251,7 @@ let TargetPrefix = "riscv" in {
// For indexed load with mask
// Input: (maskedoff, pointer, index, mask, vl, policy)
class RISCVILoadMasked
- : Intrinsic<[llvm_anyvector_ty ],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty ],
[LLVMMatchType<0>,
LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
@@ -263,7 +263,7 @@ let TargetPrefix = "riscv" in {
// For unit stride store
// Input: (vector_in, pointer, vl)
class RISCVUSStore
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty,
LLVMPointerType<LLVMMatchType<0>>,
llvm_anyint_ty],
@@ -273,7 +273,7 @@ let TargetPrefix = "riscv" in {
// For unit stride store with mask
// Input: (vector_in, pointer, mask, vl)
class RISCVUSStoreMasked
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty,
LLVMPointerType<LLVMMatchType<0>>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
@@ -284,7 +284,7 @@ let TargetPrefix = "riscv" in {
// For strided store
// Input: (vector_in, pointer, stride, vl)
class RISCVSStore
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty,
LLVMPointerType<LLVMMatchType<0>>,
llvm_anyint_ty, LLVMMatchType<1>],
@@ -294,7 +294,7 @@ let TargetPrefix = "riscv" in {
// For stride store with mask
// Input: (vector_in, pointer, stirde, mask, vl)
class RISCVSStoreMasked
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty,
LLVMPointerType<LLVMMatchType<0>>, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>],
@@ -304,7 +304,7 @@ let TargetPrefix = "riscv" in {
// For indexed store
// Input: (vector_in, pointer, index, vl)
class RISCVIStore
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty,
LLVMPointerType<LLVMMatchType<0>>,
llvm_anyint_ty, llvm_anyint_ty],
@@ -314,7 +314,7 @@ let TargetPrefix = "riscv" in {
// For indexed store with mask
// Input: (vector_in, pointer, index, mask, vl)
class RISCVIStoreMasked
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty,
LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
@@ -324,7 +324,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is the same as source vector.
// Input: (passthru, vector_in, vl)
class RISCVUnaryAAUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
@@ -332,7 +332,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is the same as first source vector (with mask).
// Input: (vector_in, vector_in, mask, vl, policy)
class RISCVUnaryAAMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<1>],
@@ -341,7 +341,7 @@ let TargetPrefix = "riscv" in {
}
// Input: (passthru, vector_in, vector_in, mask, vl)
class RISCVCompress
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -350,7 +350,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is the same as first and second source vector.
// Input: (vector_in, vector_in, vl)
class RISCVBinaryAAAUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
@@ -358,7 +358,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is the same as first and second source vector.
// Input: (passthru, vector_in, int_vector_in, vl)
class RISCVRGatherVVUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
LLVMVectorOfBitcastsToInt<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -367,7 +367,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is the same as first and second source vector.
// Input: (vector_in, vector_in, int_vector_in, vl, policy)
class RISCVRGatherVVMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<1>],
@@ -376,7 +376,7 @@ let TargetPrefix = "riscv" in {
}
// Input: (passthru, vector_in, int16_vector_in, vl)
class RISCVRGatherEI16VVUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i16_ty>,
llvm_anyint_ty],
@@ -386,7 +386,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is the same as first and second source vector.
// Input: (vector_in, vector_in, int16_vector_in, vl, policy)
class RISCVRGatherEI16VVMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i16_ty>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
@@ -398,7 +398,7 @@ let TargetPrefix = "riscv" in {
// second operand is XLen.
// Input: (passthru, vector_in, xlen_in, vl)
class RISCVGatherVXUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
LLVMMatchType<1>],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -408,7 +408,7 @@ let TargetPrefix = "riscv" in {
// Second operand is XLen.
// Input: (maskedoff, vector_in, xlen_in, mask, vl, policy)
class RISCVGatherVXMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>,
LLVMMatchType<1>],
@@ -418,7 +418,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is the same as first source vector.
// Input: (passthru, vector_in, vector_in/scalar_in, vl)
class RISCVBinaryAAXUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -428,7 +428,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is the same as first source vector (with mask).
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl, policy)
class RISCVBinaryAAXMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<2>],
@@ -440,7 +440,7 @@ let TargetPrefix = "riscv" in {
// second source operand must match the destination type or be an XLen scalar.
// Input: (passthru, vector_in, vector_in/scalar_in, vl)
class RISCVBinaryAAShiftUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -450,7 +450,7 @@ let TargetPrefix = "riscv" in {
// The second source operand must match the destination type or be an XLen scalar.
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl, policy)
class RISCVBinaryAAShiftMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<2>],
@@ -460,7 +460,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is NOT the same as first source vector.
// Input: (passthru, vector_in, vector_in/scalar_in, vl)
class RISCVBinaryABXUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -470,7 +470,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is NOT the same as first source vector (with mask).
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl, policy)
class RISCVBinaryABXMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<3>],
@@ -482,7 +482,7 @@ let TargetPrefix = "riscv" in {
// second source operand must match the destination type or be an XLen scalar.
// Input: (passthru, vector_in, vector_in/scalar_in, vl)
class RISCVBinaryABShiftUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -492,7 +492,7 @@ let TargetPrefix = "riscv" in {
// The second source operand must match the destination type or be an XLen scalar.
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl, policy)
class RISCVBinaryABShiftMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<3>],
@@ -502,7 +502,7 @@ let TargetPrefix = "riscv" in {
// For binary operations with V0 as input.
// Input: (passthru, vector_in, vector_in/scalar_in, V0, vl)
class RISCVBinaryWithV0
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty],
@@ -514,7 +514,7 @@ let TargetPrefix = "riscv" in {
// Output: (mask type output)
// Input: (vector_in, vector_in/scalar_in, V0, vl)
class RISCVBinaryMOutWithV0
- :Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+ :DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty],
@@ -526,7 +526,7 @@ let TargetPrefix = "riscv" in {
// Output: (mask type output)
// Input: (vector_in, vector_in/scalar_in, vl)
class RISCVBinaryMOut
- : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+ : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let ScalarOperand = 1;
@@ -536,7 +536,7 @@ let TargetPrefix = "riscv" in {
// Output: (mask type output)
// Input: (vector_in, vector_in/scalar_in, vl)
class RISCVCompareUnMasked
- : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+ : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let ScalarOperand = 1;
@@ -546,7 +546,7 @@ let TargetPrefix = "riscv" in {
// Output: (mask type output)
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
class RISCVCompareMasked
- : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+ : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
@@ -558,7 +558,7 @@ let TargetPrefix = "riscv" in {
// Output: (bit mask type output)
// Input: (passthru, vector_in, vl)
class RISCVClassifyUnMasked
- : Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
+ : DefaultAttrsIntrinsic<[LLVMVectorOfBitcastsToInt<0>],
[LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -568,7 +568,7 @@ let TargetPrefix = "riscv" in {
// Output: (bit mask type output)
// Input: (maskedoff, vector_in, mask, vl, policy)
class RISCVClassifyMasked
- : Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
+ : DefaultAttrsIntrinsic<[LLVMVectorOfBitcastsToInt<0>],
[LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<1>],
@@ -579,7 +579,7 @@ let TargetPrefix = "riscv" in {
// The destination vector type is the same as first source vector.
// Input: (passthru, vector_in, vector_in/scalar_in, vl)
class RISCVSaturatingBinaryAAXUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
llvm_anyint_ty],
[IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
@@ -590,7 +590,7 @@ let TargetPrefix = "riscv" in {
// The destination vector type is the same as first source vector.
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl, policy)
class RISCVSaturatingBinaryAAXMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<2>],
@@ -603,7 +603,7 @@ let TargetPrefix = "riscv" in {
// The second source operand matches the destination type or is an XLen scalar.
// Input: (passthru, vector_in, vector_in/scalar_in, vl)
class RISCVSaturatingBinaryAAShiftUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
llvm_anyint_ty],
[IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
@@ -614,7 +614,7 @@ let TargetPrefix = "riscv" in {
// The second source operand matches the destination type or is an XLen scalar.
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl, policy)
class RISCVSaturatingBinaryAAShiftMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<2>],
@@ -626,7 +626,7 @@ let TargetPrefix = "riscv" in {
// The second source operand matches the destination type or is an XLen scalar.
// Input: (passthru, vector_in, vector_in/scalar_in, vl)
class RISCVSaturatingBinaryABShiftUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
llvm_anyint_ty],
[IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
@@ -637,7 +637,7 @@ let TargetPrefix = "riscv" in {
// The second source operand matches the destination type or is an XLen scalar.
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl, policy)
class RISCVSaturatingBinaryABShiftMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<3>],
@@ -646,7 +646,7 @@ let TargetPrefix = "riscv" in {
}
// Input: (vector_in, vector_in, scalar_in, vl, policy)
class RVVSlideUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
LLVMMatchType<1>, LLVMMatchType<1>],
[ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
@@ -654,7 +654,7 @@ let TargetPrefix = "riscv" in {
}
// Input: (vector_in, vector_in, vector_in/scalar_in, mask, vl, policy)
class RVVSlideMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<1>, LLVMMatchType<1>],
@@ -664,7 +664,7 @@ let TargetPrefix = "riscv" in {
// UnMasked Vector Multiply-Add operations, its first operand can not be undef.
// Input: (vector_in, vector_in/scalar, vector_in, vl, policy)
class RISCVTernaryAAXAUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
llvm_anyint_ty, LLVMMatchType<2>],
[ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
@@ -674,7 +674,7 @@ let TargetPrefix = "riscv" in {
// Masked Vector Multiply-Add operations, its first operand can not be undef.
// Input: (vector_in, vector_in/scalar, vector_in, mask, vl, policy
class RISCVTernaryAAXAMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<2>],
@@ -685,7 +685,7 @@ let TargetPrefix = "riscv" in {
// UnMasked Widening Vector Multiply-Add operations, its first operand can not be undef.
// Input: (vector_in, vector_in/scalar, vector_in, vl, policy)
class RISCVTernaryWideUnMasked
- : Intrinsic< [llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic< [llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
llvm_anyint_ty, LLVMMatchType<3>],
[ImmArg<ArgIndex<4>>, IntrNoMem] >, RISCVVIntrinsic {
@@ -695,7 +695,7 @@ let TargetPrefix = "riscv" in {
// Masked Widening Vector Multiply-Add operations, its first operand can not be undef.
// Input: (vector_in, vector_in/scalar, vector_in, mask, vl, policy
class RISCVTernaryWideMasked
- : Intrinsic< [llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic< [llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<3>],
@@ -707,7 +707,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is the same as first and third source vector.
// Input: (vector_in, vector_in, vector_in, vl)
class RISCVReductionUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -718,7 +718,7 @@ let TargetPrefix = "riscv" in {
// The mask type come from second source vector.
// Input: (maskedoff, vector_in, vector_in, vector_in, mask, vl)
class RISCVReductionMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -728,7 +728,7 @@ let TargetPrefix = "riscv" in {
// Output: (scalar type)
// Input: (vector_in, vl)
class RISCVMaskedUnarySOutUnMasked
- : Intrinsic<[LLVMMatchType<1>],
+ : DefaultAttrsIntrinsic<[LLVMMatchType<1>],
[llvm_anyvector_ty, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1;
@@ -737,7 +737,7 @@ let TargetPrefix = "riscv" in {
// Output: (scalar type)
// Input: (vector_in, mask, vl)
class RISCVMaskedUnarySOutMasked
- : Intrinsic<[LLVMMatchType<1>],
+ : DefaultAttrsIntrinsic<[LLVMMatchType<1>],
[llvm_anyvector_ty, LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
@@ -745,7 +745,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is NOT the same as source vector.
// Input: (passthru, vector_in, vl)
class RISCVUnaryABUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
@@ -753,7 +753,7 @@ let TargetPrefix = "riscv" in {
// For destination vector type is NOT the same as source vector (with mask).
// Input: (maskedoff, vector_in, mask, vl, policy)
class RISCVUnaryABMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<2>],
@@ -764,7 +764,7 @@ let TargetPrefix = "riscv" in {
// Output: (vector)
// Input: (vector_in, vl)
class RISCVUnaryUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1;
@@ -773,7 +773,7 @@ let TargetPrefix = "riscv" in {
// Output: (mask type output)
// Input: (mask type maskedoff, mask type vector_in, mask, vl)
class RISCVMaskedUnaryMOutMasked
- : Intrinsic<[llvm_anyint_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
@@ -782,14 +782,14 @@ let TargetPrefix = "riscv" in {
// Output: (vector)
// Input: (vl)
class RISCVNullaryIntrinsic
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1;
}
// Output: (vector)
// Input: (passthru, vl)
class RISCVID
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1;
@@ -797,7 +797,7 @@ let TargetPrefix = "riscv" in {
// For Conversion unary operations.
// Input: (passthru, vector_in, vl)
class RISCVConversionUnMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
@@ -805,7 +805,7 @@ let TargetPrefix = "riscv" in {
// For Conversion unary operations with mask.
// Input: (maskedoff, vector_in, mask, vl, policy)
class RISCVConversionMasked
- : Intrinsic<[llvm_anyvector_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<2>],
@@ -816,7 +816,7 @@ let TargetPrefix = "riscv" in {
// For unit stride segment load
// Input: (passthru, pointer, vl)
class RISCVUSSegLoad<int nf>
- : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+ : DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>, llvm_anyint_ty]),
@@ -826,7 +826,7 @@ let TargetPrefix = "riscv" in {
// For unit stride segment load with mask
// Input: (maskedoff, pointer, mask, vl, policy)
class RISCVUSSegLoadMasked<int nf>
- : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+ : DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>,
@@ -843,7 +843,7 @@ let TargetPrefix = "riscv" in {
// NOTE: We model this with default memory properties since we model writing
// VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
class RISCVUSSegLoadFF<int nf>
- : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+ : DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1)), [llvm_anyint_ty]),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>, LLVMMatchType<1>]),
@@ -856,7 +856,7 @@ let TargetPrefix = "riscv" in {
// NOTE: We model this with default memory properties since we model writing
// VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
class RISCVUSSegLoadFFMasked<int nf>
- : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+ : DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1)), [llvm_anyint_ty]),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>,
@@ -870,7 +870,7 @@ let TargetPrefix = "riscv" in {
// For stride segment load
// Input: (passthru, pointer, offset, vl)
class RISCVSSegLoad<int nf>
- : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+ : DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>, llvm_anyint_ty, LLVMMatchType<1>]),
@@ -880,7 +880,7 @@ let TargetPrefix = "riscv" in {
// For stride segment load with mask
// Input: (maskedoff, pointer, offset, mask, vl, policy)
class RISCVSSegLoadMasked<int nf>
- : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+ : DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>,
@@ -895,7 +895,7 @@ let TargetPrefix = "riscv" in {
// For indexed segment load
// Input: (passthru, pointer, index, vl)
class RISCVISegLoad<int nf>
- : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+ : DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>, llvm_anyvector_ty, llvm_anyint_ty]),
@@ -905,7 +905,7 @@ let TargetPrefix = "riscv" in {
// For indexed segment load with mask
// Input: (maskedoff, pointer, index, mask, vl, policy)
class RISCVISegLoadMasked<int nf>
- : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
+ : DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>,
@@ -920,7 +920,7 @@ let TargetPrefix = "riscv" in {
// For unit stride segment store
// Input: (value, pointer, vl)
class RISCVUSSegStore<int nf>
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
!listconcat([llvm_anyvector_ty],
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[LLVMPointerToElt<0>, llvm_anyint_ty]),
@@ -930,7 +930,7 @@ let TargetPrefix = "riscv" in {
// For unit stride segment store with mask
// Input: (value, pointer, mask, vl)
class RISCVUSSegStoreMasked<int nf>
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
!listconcat([llvm_anyvector_ty],
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[LLVMPointerToElt<0>,
@@ -943,7 +943,7 @@ let TargetPrefix = "riscv" in {
// For stride segment store
// Input: (value, pointer, offset, vl)
class RISCVSSegStore<int nf>
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
!listconcat([llvm_anyvector_ty],
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[LLVMPointerToElt<0>, llvm_anyint_ty,
@@ -954,7 +954,7 @@ let TargetPrefix = "riscv" in {
// For stride segment store with mask
// Input: (value, pointer, offset, mask, vl)
class RISCVSSegStoreMasked<int nf>
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
!listconcat([llvm_anyvector_ty],
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[LLVMPointerToElt<0>, llvm_anyint_ty,
@@ -967,7 +967,7 @@ let TargetPrefix = "riscv" in {
// For indexed segment store
// Input: (value, pointer, offset, vl)
class RISCVISegStore<int nf>
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
!listconcat([llvm_anyvector_ty],
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[LLVMPointerToElt<0>, llvm_anyvector_ty,
@@ -978,7 +978,7 @@ let TargetPrefix = "riscv" in {
// For indexed segment store with mask
// Input: (value, pointer, offset, mask, vl)
class RISCVISegStoreMasked<int nf>
- : Intrinsic<[],
+ : DefaultAttrsIntrinsic<[],
!listconcat([llvm_anyvector_ty],
!listsplat(LLVMMatchType<0>, !add(nf, -1)),
[LLVMPointerToElt<0>, llvm_anyvector_ty,
@@ -1253,46 +1253,51 @@ let TargetPrefix = "riscv" in {
// Output: (vector)
// Input: (passthru, vector_in, vl)
- def int_riscv_vmv_v_v : Intrinsic<[llvm_anyvector_ty],
- [LLVMMatchType<0>, LLVMMatchType<0>,
- llvm_anyint_ty],
- [IntrNoMem]>, RISCVVIntrinsic {
+ def int_riscv_vmv_v_v : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>,
+ LLVMMatchType<0>,
+ llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
}
// Output: (vector)
// Input: (passthru, scalar, vl)
- def int_riscv_vmv_v_x : Intrinsic<[llvm_anyint_ty],
- [LLVMMatchType<0>, LLVMVectorElementType<0>,
- llvm_anyint_ty],
- [IntrNoMem]>, RISCVVIntrinsic {
+ def int_riscv_vmv_v_x : DefaultAttrsIntrinsic<[llvm_anyint_ty],
+ [LLVMMatchType<0>,
+ LLVMVectorElementType<0>,
+ llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
}
// Output: (vector)
// Input: (passthru, scalar, vl)
- def int_riscv_vfmv_v_f : Intrinsic<[llvm_anyfloat_ty],
- [LLVMMatchType<0>, LLVMVectorElementType<0>,
- llvm_anyint_ty],
- [IntrNoMem]>, RISCVVIntrinsic {
+ def int_riscv_vfmv_v_f : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
+ [LLVMMatchType<0>,
+ LLVMVectorElementType<0>,
+ llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
}
- def int_riscv_vmv_x_s : Intrinsic<[LLVMVectorElementType<0>],
- [llvm_anyint_ty],
- [IntrNoMem]>, RISCVVIntrinsic;
- def int_riscv_vmv_s_x : Intrinsic<[llvm_anyint_ty],
- [LLVMMatchType<0>, LLVMVectorElementType<0>,
- llvm_anyint_ty],
- [IntrNoMem]>, RISCVVIntrinsic {
+ def int_riscv_vmv_x_s : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+ [llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic;
+ def int_riscv_vmv_s_x : DefaultAttrsIntrinsic<[llvm_anyint_ty],
+ [LLVMMatchType<0>,
+ LLVMVectorElementType<0>,
+ llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
}
- def int_riscv_vfmv_f_s : Intrinsic<[LLVMVectorElementType<0>],
- [llvm_anyfloat_ty],
- [IntrNoMem]>, RISCVVIntrinsic;
- def int_riscv_vfmv_s_f : Intrinsic<[llvm_anyfloat_ty],
- [LLVMMatchType<0>, LLVMVectorElementType<0>,
- llvm_anyint_ty],
- [IntrNoMem]>, RISCVVIntrinsic {
+ def int_riscv_vfmv_f_s : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+ [llvm_anyfloat_ty],
+ [IntrNoMem]>, RISCVVIntrinsic;
+ def int_riscv_vfmv_s_f : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
+ [LLVMMatchType<0>,
+ LLVMVectorElementType<0>,
+ llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
}
@@ -1428,21 +1433,23 @@ let TargetPrefix = "riscv" in {
// Output: (vector)
// Input: (passthru, mask type input, vl)
- def int_riscv_viota : Intrinsic<[llvm_anyvector_ty],
- [LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_anyint_ty],
- [IntrNoMem]>, RISCVVIntrinsic {
+ def int_riscv_viota
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+ llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
}
// Output: (vector)
// Input: (maskedoff, mask type vector_in, mask, vl, policy)
- def int_riscv_viota_mask : Intrinsic<[llvm_anyvector_ty],
- [LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_anyint_ty, LLVMMatchType<1>],
- [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
+ def int_riscv_viota_mask
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+ llvm_anyint_ty, LLVMMatchType<1>],
+ [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 3;
}
// Output: (vector)
@@ -1451,11 +1458,12 @@ let TargetPrefix = "riscv" in {
// Output: (vector)
// Input: (maskedoff, mask, vl, policy)
- def int_riscv_vid_mask : Intrinsic<[llvm_anyvector_ty],
- [LLVMMatchType<0>,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_anyint_ty, LLVMMatchType<1>],
- [ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
+ def int_riscv_vid_mask
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+ llvm_anyint_ty, LLVMMatchType<1>],
+ [ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
}
@@ -1473,23 +1481,26 @@ let TargetPrefix = "riscv" in {
// Strided loads/stores for fixed vectors.
def int_riscv_masked_strided_load
- : Intrinsic<[llvm_anyvector_ty],
- [LLVMMatchType<0>, llvm_anyptr_ty,
- llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
- [NoCapture<ArgIndex<1>>, IntrReadMem]>;
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_anyptr_ty,
+ llvm_anyint_ty,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+ [NoCapture<ArgIndex<1>>, IntrReadMem]>;
def int_riscv_masked_strided_store
- : Intrinsic<[],
- [llvm_anyvector_ty, llvm_anyptr_ty,
- llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
- [NoCapture<ArgIndex<1>>, IntrWriteMem]>;
+ : DefaultAttrsIntrinsic<[],
+ [llvm_anyvector_ty, llvm_anyptr_ty,
+ llvm_anyint_ty,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+ [NoCapture<ArgIndex<1>>, IntrWriteMem]>;
// Segment loads for fixed vectors.
foreach nf = [2, 3, 4, 5, 6, 7, 8] in {
def int_riscv_seg # nf # _load
- : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
- !add(nf, -1))),
- [llvm_anyptr_ty, llvm_anyint_ty],
- [NoCapture<ArgIndex<0>>, IntrReadMem]>;
+ : DefaultAttrsIntrinsic<!listconcat([llvm_anyvector_ty],
+ !listsplat(LLVMMatchType<0>,
+ !add(nf, -1))),
+ [llvm_anyptr_ty, llvm_anyint_ty],
+ [NoCapture<ArgIndex<0>>, IntrReadMem]>;
}
} // TargetPrefix = "riscv"
@@ -1503,36 +1514,35 @@ let TargetPrefix = "riscv" in {
let TargetPrefix = "riscv" in {
class ScalarCryptoGprIntrinsicAny
- : Intrinsic<[llvm_anyint_ty],
+ : DefaultAttrsIntrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>;
class ScalarCryptoByteSelect32
- : Intrinsic<[llvm_i32_ty],
- [llvm_i32_ty, llvm_i32_ty, llvm_i8_ty],
- [IntrNoMem, IntrWillReturn, IntrSpeculatable,
- ImmArg<ArgIndex<2>>]>;
+ : DefaultAttrsIntrinsic<[llvm_i32_ty],
+ [llvm_i32_ty, llvm_i32_ty, llvm_i8_ty],
+ [IntrNoMem, IntrSpeculatable,
+ ImmArg<ArgIndex<2>>]>;
class ScalarCryptoGprGprIntrinsic32
- : Intrinsic<[llvm_i32_ty],
- [llvm_i32_ty, llvm_i32_ty],
- [IntrNoMem, IntrWillReturn, IntrSpeculatable]>;
+ : DefaultAttrsIntrinsic<[llvm_i32_ty],
+ [llvm_i32_ty, llvm_i32_ty],
+ [IntrNoMem, IntrSpeculatable]>;
class ScalarCryptoGprGprIntrinsic64
- : Intrinsic<[llvm_i64_ty],
- [llvm_i64_ty, llvm_i64_ty],
- [IntrNoMem, IntrWillReturn, IntrSpeculatable]>;
+ : DefaultAttrsIntrinsic<[llvm_i64_ty],
+ [llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem, IntrSpeculatable]>;
class ScalarCryptoGprIntrinsic64
- : Intrinsic<[llvm_i64_ty],
- [llvm_i64_ty],
- [IntrNoMem, IntrWillReturn, IntrSpeculatable]>;
+ : DefaultAttrsIntrinsic<[llvm_i64_ty],
+ [llvm_i64_ty],
+ [IntrNoMem, IntrSpeculatable]>;
class ScalarCryptoByteSelectAny
- : Intrinsic<[llvm_anyint_ty],
- [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i8_ty],
- [IntrNoMem, IntrSpeculatable, IntrWillReturn,
- ImmArg<ArgIndex<2>>]>;
+ : DefaultAttrsIntrinsic<[llvm_anyint_ty],
+ [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i8_ty],
+ [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
// Zknd
def int_riscv_aes32dsi : ScalarCryptoByteSelect32;
@@ -1552,9 +1562,10 @@ def int_riscv_aes64esm : ScalarCryptoGprGprIntrinsic64;
// Zknd & Zkne
def int_riscv_aes64ks2 : ScalarCryptoGprGprIntrinsic64;
-def int_riscv_aes64ks1i : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty],
- [IntrNoMem, IntrSpeculatable,
- IntrWillReturn, ImmArg<ArgIndex<1>>]>;
+def int_riscv_aes64ks1i : DefaultAttrsIntrinsic<[llvm_i64_ty],
+ [llvm_i64_ty, llvm_i32_ty],
+ [IntrNoMem, IntrSpeculatable,
+ ImmArg<ArgIndex<1>>]>;
// Zknh
def int_riscv_sha256sig0 : ScalarCryptoGprIntrinsicAny;
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