[PATCH] D140069: [DAGCombiner] Scalarize vectorized loads that are splatted
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 20 08:26:07 PST 2022
luke added inline comments.
================
Comment at: llvm/test/CodeGen/AArch64/arm64-vmul.ll:1227-1230
+; CHECK-NEXT: add x8, x1, #4
+; CHECK-NEXT: ldr d1, [x0]
+; CHECK-NEXT: ld1r.2s { v0 }, [x8]
+; CHECK-NEXT: fmulx.2s v0, v1, v0
----------------
@dmgreen This looks like a regression to me but I'm not familiar enough with aarch64 to really know for certain. I presume the cost of the additional add instruction outweighs any gains from a smaller load, is that correct?
(Hope I'm not bombarding you with too many questions, let me know if there's someone else I can ask!)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D140069/new/
https://reviews.llvm.org/D140069
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