[PATCH] D139411: [AAch64] Optimize muls with operands having enough zero bits.
Biplob Mishra via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 20 06:35:11 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG454997d39659: [AAch64] Optimize muls with operands having enough zero bits. (authored by bipmis).
Changed prior to commit:
https://reviews.llvm.org/D139411?vs=480436&id=484248#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D139411/new/
https://reviews.llvm.org/D139411
Files:
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
llvm/test/CodeGen/AArch64/addcarry-crash.ll
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