[PATCH] D140069: [DAGCombiner] Scalarize vectorized loads that are splatted

[Luke Lau via Phabricator via llvm-commits]

luke added a subscriber: t.p.northover.
luke added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/arm64-vmul.ll:1102-1106
+; CHECK-NEXT:    add x8, x1, #2
+; CHECK-NEXT:    ldr q1, [x0]
+; CHECK-NEXT:    ld1r.8h { v0 }, [x8]
+; CHECK-NEXT:    mul.8h v0, v1, v0
 ; CHECK-NEXT:    ret
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luke wrote:
> Regression: Can the `add` be folded in as an immediate offset to `ld1r.8h { v0 }, [x8]`?
> Same applies for the cases below
No, since the offset would actually increment the register operand. 
Should we instead check if the target is able to perform an indexed load, and bail otherwise when the offset != 0?
There's a target lowering hook called `isIndexingLegal` that seems like it could be used to check this, but no targets currently implement it, and it was added for GlobalISel: https://reviews.llvm.org/D66287
@t.p.northover would you have any thoughts on this?


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  https://reviews.llvm.org/D140069/new/

https://reviews.llvm.org/D140069