[llvm] 1ae618d - [AArch64] Name instructions in test (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 20 03:12:19 PST 2022
Author: Nikita Popov
Date: 2022-12-20T12:12:11+01:00
New Revision: 1ae618d066dae92543b52b275e7627c37b9da7ea
URL: https://github.com/llvm/llvm-project/commit/1ae618d066dae92543b52b275e7627c37b9da7ea
DIFF: https://github.com/llvm/llvm-project/commit/1ae618d066dae92543b52b275e7627c37b9da7ea.diff
LOG: [AArch64] Name instructions in test (NFC)
And regenerate check lines.
Added:
Modified:
llvm/test/CodeGen/AArch64/loop-sink.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/loop-sink.mir b/llvm/test/CodeGen/AArch64/loop-sink.mir
index 124f55bc9b9a..5ab0951350b3 100644
--- a/llvm/test/CodeGen/AArch64/loop-sink.mir
+++ b/llvm/test/CodeGen/AArch64/loop-sink.mir
@@ -4,57 +4,59 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
- @A = external dso_local global [100 x i32], align 4
%struct.A = type { i32, i32, i32, i32, i32, i32 }
+ @A = external dso_local global [100 x i32], align 4
+
define void @cant_sink_adds_call_in_block(i8* nocapture readonly %input, %struct.A* %a) {
- %1 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 1
- %2 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 2
- %3 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 3
- %4 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 4
- %5 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 5
+ bb:
+ %i = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 1
+ %i1 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 2
+ %i2 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 3
+ %i3 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 4
+ %i4 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 5
%scevgep = getelementptr i8, i8* %input, i64 1
br label %.backedge
- .backedge: ; preds = %.backedge.backedge, %0
- %lsr.iv = phi i8* [ %scevgep1, %.backedge.backedge ], [ %scevgep, %0 ]
- %6 = load i8, i8* %lsr.iv, align 1
- %7 = zext i8 %6 to i32
- switch i32 %7, label %.backedge.backedge [
- i32 0, label %8
- i32 10, label %10
- i32 20, label %11
- i32 30, label %12
- i32 40, label %13
- i32 50, label %14
+ .backedge: ; preds = %.backedge.backedge, %bb
+ %lsr.iv = phi i8* [ %scevgep1, %.backedge.backedge ], [ %scevgep, %bb ]
+ %i5 = load i8, i8* %lsr.iv, align 1
+ %i6 = zext i8 %i5 to i32
+ switch i32 %i6, label %.backedge.backedge [
+ i32 0, label %bb7
+ i32 10, label %bb9
+ i32 20, label %bb10
+ i32 30, label %bb11
+ i32 40, label %bb12
+ i32 50, label %bb13
]
- 8: ; preds = %.backedge
- %9 = bitcast %struct.A* %a to i32*
- tail call void @_Z6assignPj(i32* %9)
+ bb7: ; preds = %.backedge
+ %i8 = bitcast %struct.A* %a to i32*
+ tail call void @_Z6assignPj(i32* %i8)
br label %.backedge.backedge
- 10: ; preds = %.backedge
- tail call void @_Z6assignPj(i32* %1)
+ bb9: ; preds = %.backedge
+ tail call void @_Z6assignPj(i32* %i)
br label %.backedge.backedge
- 11: ; preds = %.backedge
- tail call void @_Z6assignPj(i32* %2)
+ bb10: ; preds = %.backedge
+ tail call void @_Z6assignPj(i32* %i1)
br label %.backedge.backedge
- 12: ; preds = %.backedge
- tail call void @_Z6assignPj(i32* %3)
+ bb11: ; preds = %.backedge
+ tail call void @_Z6assignPj(i32* %i2)
br label %.backedge.backedge
- 13: ; preds = %.backedge
- tail call void @_Z6assignPj(i32* %4)
+ bb12: ; preds = %.backedge
+ tail call void @_Z6assignPj(i32* %i3)
br label %.backedge.backedge
- 14: ; preds = %.backedge
- tail call void @_Z6assignPj(i32* %5)
+ bb13: ; preds = %.backedge
+ tail call void @_Z6assignPj(i32* %i4)
br label %.backedge.backedge
- .backedge.backedge: ; preds = %14, %13, %12, %11, %10, %8, %.backedge
+ .backedge.backedge: ; preds = %bb13, %bb12, %bb11, %bb10, %bb9, %bb7, %.backedge
%scevgep1 = getelementptr i8, i8* %lsr.iv, i64 1
br label %.backedge
}
@@ -65,7 +67,7 @@
br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
+ %i = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
%call0 = tail call i32 @use(i32 %n)
br label %for.body
@@ -76,7 +78,7 @@
for.body: ; preds = %for.body, %for.body.preheader
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
- %div = sdiv i32 %sum.065, %0
+ %div = sdiv i32 %sum.065, %i
%lsr.iv.next = add i32 %lsr.iv, -1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
@@ -88,8 +90,8 @@
br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
- %call0 = tail call i32 @use(i32 %0)
+ %i = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
+ %call0 = tail call i32 @use(i32 %i)
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
@@ -99,7 +101,7 @@
for.body: ; preds = %for.body, %for.body.preheader
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
- %div = sdiv i32 %sum.065, %0
+ %div = sdiv i32 %sum.065, %i
%lsr.iv.next = add i32 %lsr.iv, -1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
@@ -111,12 +113,12 @@
br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
+ %i = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
- %use.outside.loop = phi i32 [ 0, %entry ], [ %0, %for.body ]
+ %use.outside.loop = phi i32 [ 0, %entry ], [ %i, %for.body ]
%call = tail call i32 @use(i32 %use.outside.loop)
ret i32 %sum.0.lcssa
@@ -135,7 +137,7 @@
br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
+ %i = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
@@ -145,29 +147,29 @@
for.body: ; preds = %for.body, %for.body.preheader
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
- %div = sdiv i32 %sum.065, %0
+ %div = sdiv i32 %sum.065, %i
%lsr.iv.next = add i32 %lsr.iv, -1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
- define dso_local void @sink_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32 %n) local_unnamed_addr #0 {
+ define dso_local void @sink_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32 %n) local_unnamed_addr {
entry:
- %0 = load i32, i32* %read, align 4, !tbaa !6
+ %i = load i32, i32* %read, align 4, !tbaa !0
%cmp10 = icmp sgt i32 %n, 0
br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %1 = add i32 %0, 42
+ %i1 = add i32 %i, 42
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
- store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !6
+ store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !0
ret void
- for.body: ; preds = %for.body.preheader, %for.body
- %lsr.iv1 = phi i32 [ %1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
+ for.body: ; preds = %for.body, %for.body.preheader
+ %lsr.iv1 = phi i32 [ %i1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.011 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.011, %lsr.iv1
@@ -177,70 +179,70 @@
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
- define dso_local void @store_after_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32* nocapture %store, i32 %n) local_unnamed_addr #0 {
+ define dso_local void @store_after_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32* nocapture %store, i32 %n) local_unnamed_addr {
entry:
- %0 = load i32, i32* %read, align 4, !tbaa !6
+ %i = load i32, i32* %read, align 4, !tbaa !0
%cmp10 = icmp sgt i32 %n, 0
br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %1 = add i32 %0, 42
- store i32 43, i32* %store, align 4, !tbaa !6
+ %i1 = add i32 %i, 42
+ store i32 43, i32* %store, align 4, !tbaa !0
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
- store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !6
+ store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !0
ret void
- for.body: ; preds = %for.body.preheader, %for.body
- %lsr.iv1 = phi i32 [ %1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
+ for.body: ; preds = %for.body, %for.body.preheader
+ %lsr.iv1 = phi i32 [ %i1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.011 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.011, %lsr.iv1
%lsr.iv.next = add i32 %lsr.iv, -1
%lsr.iv.next2 = add i32 %lsr.iv1, 1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
- br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !10
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !4
}
- define dso_local void @aliased_store_after_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32* nocapture %store, i32 %n) local_unnamed_addr #0 {
+ define dso_local void @aliased_store_after_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32* nocapture %store, i32 %n) local_unnamed_addr {
entry:
- %0 = load i32, i32* %read, align 4, !tbaa !6
+ %i = load i32, i32* %read, align 4, !tbaa !0
%cmp10 = icmp sgt i32 %n, 0
br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
- %1 = add i32 %0, 42
- store i32 43, i32* %read, align 4, !tbaa !6
+ %i1 = add i32 %i, 42
+ store i32 43, i32* %read, align 4, !tbaa !0
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
- store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !6
+ store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !0
ret void
- for.body: ; preds = %for.body.preheader, %for.body
- %lsr.iv1 = phi i32 [ %1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
+ for.body: ; preds = %for.body, %for.body.preheader
+ %lsr.iv1 = phi i32 [ %i1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.011 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.011, %lsr.iv1
%lsr.iv.next = add i32 %lsr.iv, -1
%lsr.iv.next2 = add i32 %lsr.iv1, 1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
- br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !10
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !4
}
-
declare i32 @use(i32)
+
declare void @_Z6assignPj(i32*)
- !6 = !{!7, !7, i64 0}
- !7 = !{!"int", !8, i64 0}
- !8 = !{!"omnipotent char", !9, i64 0}
- !9 = !{!"Simple C/C++ TBAA"}
- !10 = distinct !{!10, !11}
- !11 = !{!"llvm.loop.mustprogress"}
+ !0 = !{!1, !1, i64 0}
+ !1 = !{!"int", !2, i64 0}
+ !2 = !{!"omnipotent char", !3, i64 0}
+ !3 = !{!"Simple C/C++ TBAA"}
+ !4 = distinct !{!4, !5}
+ !5 = !{!"llvm.loop.mustprogress"}
...
---
@@ -321,83 +323,102 @@ jumpTable:
'%bb.8', '%bb.8', '%bb.7' ]
body: |
; CHECK-LABEL: name: cant_sink_adds_call_in_block
- ; CHECK: bb.0 (%ir-block.0):
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: liveins: $x0, $x1
- ; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $x1
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0
- ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 4, 0
- ; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY [[ADDXri]]
- ; CHECK: [[ADDXri1:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 8, 0
- ; CHECK: [[COPY3:%[0-9]+]]:gpr64all = COPY [[ADDXri1]]
- ; CHECK: [[ADDXri2:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 12, 0
- ; CHECK: [[COPY4:%[0-9]+]]:gpr64all = COPY [[ADDXri2]]
- ; CHECK: [[ADDXri3:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 16, 0
- ; CHECK: [[COPY5:%[0-9]+]]:gpr64all = COPY [[ADDXri3]]
- ; CHECK: [[ADDXri4:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 20, 0
- ; CHECK: [[COPY6:%[0-9]+]]:gpr64all = COPY [[ADDXri4]]
- ; CHECK: [[ADDXri5:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 1, 0
- ; CHECK: [[COPY7:%[0-9]+]]:gpr64all = COPY [[ADDXri5]]
- ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
- ; CHECK: bb.1..backedge:
- ; CHECK: successors: %bb.9(0x09249249), %bb.2(0x76db6db7)
- ; CHECK: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY7]], %bb.0, %7, %bb.9
- ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[PHI]], 0 :: (load (s8) from %ir.lsr.iv)
- ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, killed [[LDRBBui]], %subreg.sub_32
- ; CHECK: [[COPY8:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri killed [[COPY8]], 50, 0, implicit-def $nzcv
- ; CHECK: Bcc 8, %bb.9, implicit $nzcv
- ; CHECK: bb.2..backedge:
- ; CHECK: successors: %bb.3(0x13b13b14), %bb.9(0x09d89d8a), %bb.4(0x13b13b14), %bb.5(0x13b13b14), %bb.6(0x13b13b14), %bb.7(0x13b13b14), %bb.8(0x13b13b14)
- ; CHECK: early-clobber %21:gpr64, early-clobber %22:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
- ; CHECK: BR killed %21
- ; CHECK: bb.3 (%ir-block.8):
- ; CHECK: successors: %bb.9(0x80000000)
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $x0 = COPY [[COPY]]
- ; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
- ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: B %bb.9
- ; CHECK: bb.4 (%ir-block.10):
- ; CHECK: successors: %bb.9(0x80000000)
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $x0 = COPY [[COPY2]]
- ; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
- ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: B %bb.9
- ; CHECK: bb.5 (%ir-block.11):
- ; CHECK: successors: %bb.9(0x80000000)
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $x0 = COPY [[COPY3]]
- ; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
- ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: B %bb.9
- ; CHECK: bb.6 (%ir-block.12):
- ; CHECK: successors: %bb.9(0x80000000)
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $x0 = COPY [[COPY4]]
- ; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
- ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: B %bb.9
- ; CHECK: bb.7 (%ir-block.13):
- ; CHECK: successors: %bb.9(0x80000000)
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $x0 = COPY [[COPY5]]
- ; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
- ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: B %bb.9
- ; CHECK: bb.8 (%ir-block.14):
- ; CHECK: successors: %bb.9(0x80000000)
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $x0 = COPY [[COPY6]]
- ; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
- ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: bb.9..backedge.backedge:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[ADDXri6:%[0-9]+]]:gpr64sp = ADDXri [[PHI]], 1, 0
- ; CHECK: [[COPY9:%[0-9]+]]:gpr64all = COPY [[ADDXri6]]
- ; CHECK: B %bb.1
- bb.0 (%ir-block.0):
+ ; CHECK: bb.0.bb:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 4, 0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[ADDXri]]
+ ; CHECK-NEXT: [[ADDXri1:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 8, 0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64all = COPY [[ADDXri1]]
+ ; CHECK-NEXT: [[ADDXri2:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 12, 0
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64all = COPY [[ADDXri2]]
+ ; CHECK-NEXT: [[ADDXri3:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 16, 0
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr64all = COPY [[ADDXri3]]
+ ; CHECK-NEXT: [[ADDXri4:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 20, 0
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr64all = COPY [[ADDXri4]]
+ ; CHECK-NEXT: [[ADDXri5:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 1, 0
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr64all = COPY [[ADDXri5]]
+ ; CHECK-NEXT: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1..backedge:
+ ; CHECK-NEXT: successors: %bb.9(0x09249249), %bb.2(0x76db6db7)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY7]], %bb.0, %7, %bb.9
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[PHI]], 0 :: (load (s8) from %ir.lsr.iv)
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, killed [[LDRBBui]], %subreg.sub_32
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri killed [[COPY8]], 50, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 8, %bb.9, implicit $nzcv
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2..backedge:
+ ; CHECK-NEXT: successors: %bb.3(0x13b13b14), %bb.9(0x09d89d8a), %bb.4(0x13b13b14), %bb.5(0x13b13b14), %bb.6(0x13b13b14), %bb.7(0x13b13b14), %bb.8(0x13b13b14)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber %21:gpr64, early-clobber %22:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
+ ; CHECK-NEXT: BR killed %21
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.bb7:
+ ; CHECK-NEXT: successors: %bb.9(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $x0 = COPY [[COPY]]
+ ; CHECK-NEXT: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: B %bb.9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4.bb9:
+ ; CHECK-NEXT: successors: %bb.9(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $x0 = COPY [[COPY2]]
+ ; CHECK-NEXT: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: B %bb.9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5.bb10:
+ ; CHECK-NEXT: successors: %bb.9(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $x0 = COPY [[COPY3]]
+ ; CHECK-NEXT: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: B %bb.9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6.bb11:
+ ; CHECK-NEXT: successors: %bb.9(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $x0 = COPY [[COPY4]]
+ ; CHECK-NEXT: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: B %bb.9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7.bb12:
+ ; CHECK-NEXT: successors: %bb.9(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $x0 = COPY [[COPY5]]
+ ; CHECK-NEXT: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: B %bb.9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.8.bb13:
+ ; CHECK-NEXT: successors: %bb.9(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $x0 = COPY [[COPY6]]
+ ; CHECK-NEXT: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.9..backedge.backedge:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADDXri6:%[0-9]+]]:gpr64sp = ADDXri [[PHI]], 1, 0
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr64all = COPY [[ADDXri6]]
+ ; CHECK-NEXT: B %bb.1
+ bb.0 (%ir-block.bb):
successors: %bb.1(0x80000000)
liveins: $x0, $x1
@@ -433,7 +454,7 @@ body: |
early-clobber %21:gpr64, early-clobber %22:gpr64sp = JumpTableDest32 %20, %16, %jump-table.0
BR killed %21
- bb.2 (%ir-block.8):
+ bb.2 (%ir-block.bb7):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
@@ -442,7 +463,7 @@ body: |
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
- bb.3 (%ir-block.10):
+ bb.3 (%ir-block.bb9):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
@@ -451,7 +472,7 @@ body: |
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
- bb.4 (%ir-block.11):
+ bb.4 (%ir-block.bb10):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
@@ -460,7 +481,7 @@ body: |
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
- bb.5 (%ir-block.12):
+ bb.5 (%ir-block.bb11):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
@@ -469,7 +490,7 @@ body: |
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
- bb.6 (%ir-block.13):
+ bb.6 (%ir-block.bb12):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
@@ -478,7 +499,7 @@ body: |
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
- bb.7 (%ir-block.14):
+ bb.7 (%ir-block.bb13):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
@@ -548,35 +569,41 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: load_not_safe_to_move_consecutive_call
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1.for.body.preheader:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
- ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $w0 = COPY [[COPY]]
- ; CHECK: BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
- ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: B %bb.3
- ; CHECK: bb.2.for.cond.cleanup:
- ; CHECK: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
- ; CHECK: $w0 = COPY [[PHI]]
- ; CHECK: RET_ReallyLR implicit $w0
- ; CHECK: bb.3.for.body:
- ; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
- ; CHECK: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
- ; CHECK: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
- ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
- ; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
- ; CHECK: Bcc 0, %bb.2, implicit $nzcv
- ; CHECK: B %bb.3
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.body.preheader:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $w0 = COPY [[COPY]]
+ ; CHECK-NEXT: BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.cond.cleanup:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
+ ; CHECK-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.body:
+ ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
+ ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
+ ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
+ ; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+ ; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $w0
@@ -669,35 +696,41 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: load_not_safe_to_move_consecutive_call_use
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1.for.body.preheader:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
- ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $w0 = COPY [[LDRWui]]
- ; CHECK: BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
- ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: B %bb.3
- ; CHECK: bb.2.for.cond.cleanup:
- ; CHECK: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
- ; CHECK: $w0 = COPY [[PHI]]
- ; CHECK: RET_ReallyLR implicit $w0
- ; CHECK: bb.3.for.body:
- ; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
- ; CHECK: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
- ; CHECK: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
- ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
- ; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
- ; CHECK: Bcc 0, %bb.2, implicit $nzcv
- ; CHECK: B %bb.3
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.body.preheader:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $w0 = COPY [[LDRWui]]
+ ; CHECK-NEXT: BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.cond.cleanup:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
+ ; CHECK-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.body:
+ ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
+ ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
+ ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
+ ; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+ ; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $w0
@@ -793,42 +826,52 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: cant_sink_use_outside_loop
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 10, %bb.1, implicit $nzcv
- ; CHECK: bb.4:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY $wzr
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
- ; CHECK: B %bb.2
- ; CHECK: bb.1.for.body.preheader:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
- ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32all = COPY [[LDRWui]]
- ; CHECK: B %bb.3
- ; CHECK: bb.2.for.cond.cleanup:
- ; CHECK: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.4, %5, %bb.5
- ; CHECK: [[PHI1:%[0-9]+]]:gpr32all = PHI [[COPY2]], %bb.4, [[COPY3]], %bb.5
- ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $w0 = COPY [[PHI1]]
- ; CHECK: BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
- ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
- ; CHECK: $w0 = COPY [[PHI]]
- ; CHECK: RET_ReallyLR implicit $w0
- ; CHECK: bb.3.for.body:
- ; CHECK: successors: %bb.5(0x04000000), %bb.3(0x7c000000)
- ; CHECK: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %6, %bb.3
- ; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
- ; CHECK: [[COPY4:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
- ; CHECK: Bcc 1, %bb.3, implicit $nzcv
- ; CHECK: bb.5:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
- ; CHECK: [[COPY5:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
- ; CHECK: B %bb.2
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.4(0x30000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 10, %bb.1, implicit $nzcv
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY $wzr
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.body.preheader:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY [[LDRWui]]
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.cond.cleanup:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.4, %5, %bb.5
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr32all = PHI [[COPY2]], %bb.4, [[COPY3]], %bb.5
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $w0 = COPY [[PHI1]]
+ ; CHECK-NEXT: BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ ; CHECK-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.body:
+ ; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %6, %bb.3
+ ; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+ ; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
+ ; CHECK-NEXT: B %bb.2
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $w0
@@ -923,31 +966,37 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: use_is_not_a_copy
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $w0
- ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1.for.body.preheader:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
- ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
- ; CHECK: B %bb.3
- ; CHECK: bb.2.for.cond.cleanup:
- ; CHECK: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
- ; CHECK: $w0 = COPY [[PHI]]
- ; CHECK: RET_ReallyLR implicit $w0
- ; CHECK: bb.3.for.body:
- ; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
- ; CHECK: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
- ; CHECK: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
- ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
- ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
- ; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
- ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
- ; CHECK: Bcc 0, %bb.2, implicit $nzcv
- ; CHECK: B %bb.3
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.body.preheader:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.cond.cleanup:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
+ ; CHECK-NEXT: $w0 = COPY [[PHI]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.body:
+ ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
+ ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
+ ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
+ ; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+ ; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $w0
@@ -1043,37 +1092,43 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: sink_add
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $x0, $x1, $w2
- ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w2
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1.for.body.preheader:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY2]], 0 :: (load (s32) from %ir.read, !tbaa !0)
- ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
- ; CHECK: [[COPY3:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
- ; CHECK: B %bb.3
- ; CHECK: bb.2.for.cond.cleanup:
- ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
- ; CHECK: STRWui [[PHI]], [[COPY1]], 0 :: (store (s32) into %ir.write, !tbaa !0)
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.for.body:
- ; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
- ; CHECK: [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY3]], %bb.1, %8, %bb.3
- ; CHECK: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
- ; CHECK: [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
- ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
- ; CHECK: [[COPY4:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
- ; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
- ; CHECK: [[COPY5:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
- ; CHECK: [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
- ; CHECK: [[COPY6:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
- ; CHECK: Bcc 0, %bb.2, implicit $nzcv
- ; CHECK: B %bb.3
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $x0, $x1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w2
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.body.preheader:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY2]], 0 :: (load (s32) from %ir.read, !tbaa !0)
+ ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.cond.cleanup:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
+ ; CHECK-NEXT: STRWui [[PHI]], [[COPY1]], 0 :: (store (s32) into %ir.write, !tbaa !0)
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.body:
+ ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY3]], %bb.1, %8, %bb.3
+ ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
+ ; CHECK-NEXT: [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
+ ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
+ ; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+ ; CHECK-NEXT: [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
+ ; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1, $w2
@@ -1081,7 +1136,7 @@ body: |
%11:gpr32common = COPY $w2
%10:gpr64common = COPY $x1
%9:gpr64common = COPY $x0
- %12:gpr32common = LDRWui %9, 0 :: (load (s32) from %ir.read, !tbaa !6)
+ %12:gpr32common = LDRWui %9, 0 :: (load (s32) from %ir.read, !tbaa !0)
%13:gpr32 = SUBSWri %11, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
@@ -1095,7 +1150,7 @@ body: |
bb.2.for.cond.cleanup:
%2:gpr32 = PHI %11, %bb.0, %6, %bb.3
- STRWui %2, %10, 0 :: (store (s32) into %ir.write, !tbaa !6)
+ STRWui %2, %10, 0 :: (store (s32) into %ir.write, !tbaa !0)
RET_ReallyLR
bb.3.for.body:
@@ -1178,40 +1233,46 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: store_after_add
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $x0, $x1, $x2, $w3
- ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w3
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY $x2
- ; CHECK: [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
- ; CHECK: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1.for.body.preheader:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY3]], 0 :: (load (s32) from %ir.read, !tbaa !0)
- ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
- ; CHECK: [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
- ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 43
- ; CHECK: STRWui killed [[MOVi32imm]], [[COPY1]], 0 :: (store (s32) into %ir.store, !tbaa !0)
- ; CHECK: B %bb.3
- ; CHECK: bb.2.for.cond.cleanup:
- ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
- ; CHECK: STRWui [[PHI]], [[COPY2]], 0 :: (store (s32) into %ir.write, !tbaa !0)
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.for.body:
- ; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
- ; CHECK: [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY4]], %bb.1, %8, %bb.3
- ; CHECK: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
- ; CHECK: [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
- ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
- ; CHECK: [[COPY5:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
- ; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
- ; CHECK: [[COPY6:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
- ; CHECK: [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
- ; CHECK: [[COPY7:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
- ; CHECK: Bcc 0, %bb.2, implicit $nzcv
- ; CHECK: B %bb.3
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $w3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.body.preheader:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY3]], 0 :: (load (s32) from %ir.read, !tbaa !0)
+ ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 43
+ ; CHECK-NEXT: STRWui killed [[MOVi32imm]], [[COPY1]], 0 :: (store (s32) into %ir.store, !tbaa !0)
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.cond.cleanup:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
+ ; CHECK-NEXT: STRWui [[PHI]], [[COPY2]], 0 :: (store (s32) into %ir.write, !tbaa !0)
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.body:
+ ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY4]], %bb.1, %8, %bb.3
+ ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
+ ; CHECK-NEXT: [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
+ ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
+ ; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+ ; CHECK-NEXT: [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
+ ; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1, $x2, $w3
@@ -1220,7 +1281,7 @@ body: |
%11:gpr64common = COPY $x2
%10:gpr64common = COPY $x1
%9:gpr64common = COPY $x0
- %13:gpr32common = LDRWui %9, 0 :: (load (s32) from %ir.read, !tbaa !6)
+ %13:gpr32common = LDRWui %9, 0 :: (load (s32) from %ir.read, !tbaa !0)
%15:gpr32 = SUBSWri %12, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
@@ -1231,12 +1292,12 @@ body: |
%16:gpr32sp = ADDWri %13, 42, 0
%1:gpr32all = COPY %16
%14:gpr32 = MOVi32imm 43
- STRWui killed %14, %11, 0 :: (store (s32) into %ir.store, !tbaa !6)
+ STRWui killed %14, %11, 0 :: (store (s32) into %ir.store, !tbaa !0)
B %bb.3
bb.2.for.cond.cleanup:
%2:gpr32 = PHI %12, %bb.0, %6, %bb.3
- STRWui %2, %10, 0 :: (store (s32) into %ir.write, !tbaa !6)
+ STRWui %2, %10, 0 :: (store (s32) into %ir.write, !tbaa !0)
RET_ReallyLR
bb.3.for.body:
@@ -1319,40 +1380,46 @@ machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: aliased_store_after_add
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
- ; CHECK: liveins: $x0, $x1, $x2, $w3
- ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w3
- ; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY $x2
- ; CHECK: [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
- ; CHECK: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
- ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
- ; CHECK: Bcc 11, %bb.2, implicit $nzcv
- ; CHECK: B %bb.1
- ; CHECK: bb.1.for.body.preheader:
- ; CHECK: successors: %bb.3(0x80000000)
- ; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY3]], 0 :: (load (s32) from %ir.read, !tbaa !0)
- ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
- ; CHECK: [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
- ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 43
- ; CHECK: STRWui killed [[MOVi32imm]], [[COPY3]], 0 :: (store (s32) into %ir.read, !tbaa !0)
- ; CHECK: B %bb.3
- ; CHECK: bb.2.for.cond.cleanup:
- ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
- ; CHECK: STRWui [[PHI]], [[COPY2]], 0 :: (store (s32) into %ir.write, !tbaa !0)
- ; CHECK: RET_ReallyLR
- ; CHECK: bb.3.for.body:
- ; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
- ; CHECK: [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY4]], %bb.1, %8, %bb.3
- ; CHECK: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
- ; CHECK: [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
- ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
- ; CHECK: [[COPY5:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
- ; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
- ; CHECK: [[COPY6:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
- ; CHECK: [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
- ; CHECK: [[COPY7:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
- ; CHECK: Bcc 0, %bb.2, implicit $nzcv
- ; CHECK: B %bb.3
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: liveins: $x0, $x1, $x2, $w3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: Bcc 11, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.for.body.preheader:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY3]], 0 :: (load (s32) from %ir.read, !tbaa !0)
+ ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 43
+ ; CHECK-NEXT: STRWui killed [[MOVi32imm]], [[COPY3]], 0 :: (store (s32) into %ir.read, !tbaa !0)
+ ; CHECK-NEXT: B %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.for.cond.cleanup:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
+ ; CHECK-NEXT: STRWui [[PHI]], [[COPY2]], 0 :: (store (s32) into %ir.write, !tbaa !0)
+ ; CHECK-NEXT: RET_ReallyLR
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3.for.body:
+ ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY4]], %bb.1, %8, %bb.3
+ ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
+ ; CHECK-NEXT: [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
+ ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
+ ; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+ ; CHECK-NEXT: [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
+ ; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1, $x2, $w3
@@ -1361,7 +1428,7 @@ body: |
%11:gpr64common = COPY $x2
%10:gpr64common = COPY $x1
%9:gpr64common = COPY $x0
- %13:gpr32common = LDRWui %9, 0 :: (load (s32) from %ir.read, !tbaa !6)
+ %13:gpr32common = LDRWui %9, 0 :: (load (s32) from %ir.read, !tbaa !0)
%15:gpr32 = SUBSWri %12, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
@@ -1372,12 +1439,12 @@ body: |
%16:gpr32sp = ADDWri %13, 42, 0
%1:gpr32all = COPY %16
%14:gpr32 = MOVi32imm 43
- STRWui killed %14, %9, 0 :: (store (s32) into %ir.read, !tbaa !6)
+ STRWui killed %14, %9, 0 :: (store (s32) into %ir.read, !tbaa !0)
B %bb.3
bb.2.for.cond.cleanup:
%2:gpr32 = PHI %12, %bb.0, %6, %bb.3
- STRWui %2, %10, 0 :: (store (s32) into %ir.write, !tbaa !6)
+ STRWui %2, %10, 0 :: (store (s32) into %ir.write, !tbaa !0)
RET_ReallyLR
bb.3.for.body:
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