[PATCH] D140297: [AArch64] Add RSHRN and RSHRN2 patterns
Sam Tebbs via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 20 02:30:03 PST 2022
samtebbs added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18000
+ SDValue Imm =
+ DAG.getConstant(1LLU << (N->getConstantOperandVal(2) - 1), DL, VT);
+ SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(1), Imm);
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is it possible for the shift amount here to be greater than `VT.getScalarSizeInBits() / 2` and so not be selected by `SelectRoundingVLShr`? If it is possible then a check here would be good.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D140297/new/
https://reviews.llvm.org/D140297
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