[llvm] 36179ec - [RISCV] Replace i64:$r in tablegen patterns with GPR:$r. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-12-19T20:52:33-08:00
New Revision: 36179ec2187a8cff935d57b6fc2d1a7585b99fcd

URL: https://github.com/llvm/llvm-project/commit/36179ec2187a8cff935d57b6fc2d1a7585b99fcd
DIFF: https://github.com/llvm/llvm-project/commit/36179ec2187a8cff935d57b6fc2d1a7585b99fcd.diff

LOG: [RISCV] Replace i64:$r in tablegen patterns with GPR:$r. NFC

It's much more common to use a register class rather than a type.

Add an additional i64 cast to the patterns where needed to avoid
increasing isel table size.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
index 262df67c370a..b4e28e6fc3d6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
@@ -29,32 +29,32 @@ def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
            Sched<[WriteIALU, ReadIALU, ReadIALU]>;
 
 multiclass XVentanaCondops_pats<SDPatternOperator Op, RVInst MI> {
-  def: Pat<(select i64:$rc, (Op i64:$rs1, i64:$rs2), i64:$rs1),
-           (MI $rs1, (VT_MASKC $rs2, $rc))>;
-  def: Pat<(select i64:$rc, i64:$rs1, (Op i64:$rs1, i64:$rs2)),
-           (MI $rs1, (VT_MASKCN $rs2, $rc))>;
+  def : Pat<(i64 (select GPR:$rc, (Op GPR:$rs1, GPR:$rs2), GPR:$rs1)),
+            (MI $rs1, (VT_MASKC $rs2, $rc))>;
+  def : Pat<(i64 (select GPR:$rc, GPR:$rs1, (Op GPR:$rs1, GPR:$rs2))),
+            (MI $rs1, (VT_MASKCN $rs2, $rc))>;
 }
 
 let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
 // Directly use MASKC/MASKCN in case of any of the operands being 0.
-def: Pat<(select i64:$rc, i64:$rs1, (i64 0)),
-         (VT_MASKC $rs1, $rc)>;
-def: Pat<(select i64:$rc, (i64 0), i64:$rs1),
-         (VT_MASKCN $rs1, $rc)>;
+def : Pat<(select GPR:$rc, GPR:$rs1, (i64 0)),
+          (VT_MASKC $rs1, $rc)>;
+def : Pat<(select GPR:$rc, (i64 0), GPR:$rs1),
+          (VT_MASKCN $rs1, $rc)>;
 
 // Conditional operations patterns.
-defm: XVentanaCondops_pats<add, ADD>;
-defm: XVentanaCondops_pats<sub, SUB>;
-defm: XVentanaCondops_pats<or, OR>;
-defm: XVentanaCondops_pats<xor, XOR>;
+defm : XVentanaCondops_pats<add, ADD>;
+defm : XVentanaCondops_pats<sub, SUB>;
+defm : XVentanaCondops_pats<or, OR>;
+defm : XVentanaCondops_pats<xor, XOR>;
 
 // Conditional AND operation patterns.
-def: Pat<(select i64:$rc, (and i64:$rs1, i64:$rs2), i64:$rs1),
-         (OR (AND $rs1, $rs2), (VT_MASKCN $rs1, $rc))>;
-def: Pat<(select i64:$rc, i64:$rs1, (and i64:$rs1, i64:$rs2)),
-         (OR (AND $rs1, $rs2), (VT_MASKC $rs1, $rc))>;
+def : Pat<(i64 (select GPR:$rc, (and GPR:$rs1, GPR:$rs2), GPR:$rs1)),
+          (OR (AND $rs1, $rs2), (VT_MASKCN $rs1, $rc))>;
+def : Pat<(i64 (select GPR:$rc, GPR:$rs1, (and GPR:$rs1, GPR:$rs2))),
+          (OR (AND $rs1, $rs2), (VT_MASKC $rs1, $rc))>;
 
 // Basic select pattern that selects between 2 registers.
-def: Pat<(select i64:$rc, i64:$rs1, i64:$rs2),
-         (OR (VT_MASKC $rs1, $rc), (VT_MASKCN $rs2, $rc))>;
+def : Pat<(i64 (select GPR:$rc, GPR:$rs1, GPR:$rs2)),
+          (OR (VT_MASKC $rs1, $rc), (VT_MASKCN $rs2, $rc))>;
 } // Predicates = [IsRV64, HasVendorXVentanaCondOps]